| LSI Specification |
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| BIT | Bit Name |
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| 0 | Indicates that the device is not in forced sleep. |
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| 4 | sleep |
| Read |
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| 1 | Indicates that the device is in forced sleep | by accepting “Start sleep” (01h) | ||||
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| 0 | Indicates that no data is stored in ASYNC receive specific buffer. | ||
| 3 | data req |
| Read |
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| 1 | Indicates that data is stored in ASYNC receive specific buffer. | ||
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| recv busy |
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| 0 | Indicates that packet receive is not in busy mode. |
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| 2 |
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| Note 2) |
| 1 | Indicates that packet receive is in busy mode | due to receipt of Asynchronous | |||
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| packet and |
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| 0 | Indicates that node is not the cycle master now. |
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| 1 | cmstr |
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| 1 | Node is the cycle master now. |
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| 0 | Interrupt indicate register does not have interrupt. |
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| 0 | INT |
| Read |
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| 1 | Interrupt indicate register has interrupt. |
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Note 1) IEEE1394 block is in internal reset status until integrated PLL is locked after turning the power ON. PHY layer and Link layer do not operate during this period.
Note 2) In case that Asynchronous packet addressed to this node is received with this Bit indicate ‘1’, it transmits “ack busy X”.
Rev.1.0 | 30 | Fujitsu VLSI |
