LSI Specification | MB86617A |
<Flow chart before bus reset completion
<Host>
Read Bus reset detected (INT4) interrupt.
Read Bus reset completed (INT3)
interrupt.
Read Bus reset completed (INT3)
interrupt.
<Device>
Start bus reset.
Report Bus reset detected (INT4)
interrupt. (assert XINT)
| |
‘1’ |
|
‘0’ |
|
Bus reset completed . | No |
| |
Yes |
|
Report Bus reset completed | (INT3) |
interrupt. |
|
END |
|
Set FIFO according to FIFO mode. Clear Asynchronous receive buffer.
(Note 1)
recv busy bit=0
Store received |
Asynchronous receive buffer. |
Bus reset completed. |
No |
Yes |
Report Bus reset completed (INT3)
(assert XINT) interrupt.
.
recv busy bit=1
END
Figure 11.2.1.1 Flow example for Self-ID packet receiving before bus reset completion
Rev.1.0 | 116 | Fujitsu VLSI |
