LSI Specification
MB86617A
Rev.1.0 Fujitsu VLSI
55
7.21. Late Packet Decision Range Setting Register [A]
Late packet decision range setting register [A] is the register that sets Late decision range of source packet to be transmitted by bridge -Ach.
AD R/W Bit
15 Bit
14 Bit
13 Bit
12 Bit
11 Bit
10 Bit
9 Bit
8 Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
40h R/W late range-A
Initial Value “0000 h”
BIT Bit Name Action Value Function
15 - 8 Write in Late packet decision range.
Setting range is 0h to FFh (unit: 125µS).
7 - 0
late range-A Read/
Write -
Write in Late packet decision range.
Setting range is 0h to C0h (unit: 16/24.576MHz).
Note)
Late packet decision is performed by comparing the time difference between SPH (Source Packet Header) and CTR (Cycle Time Monitor).
-Transmit:
Packet is transmitted normally when calculation result of “SPH” minus “CTR” for source packet transmitted from Bridhe-Ach is within the
“late range-A + ‘0000’h”.
If it is out of range, Late packet process is performed. The packet concerned is deleted and transmit late is reported.
Set the upper 16 bit of the setting value for transmit offset setting register[A] (14h to 16h).
-Receive:
Received packet is output at the point of “SPH = CTR” when calculation result of “SPH” minus “CTR” for source packet received at
Bridhe-Ach is within the “late range-A + ‘0000’h” (the value this register is shifted 4 bits to the left).
If it is out of range, Late packet process is performed. The packet concerned is deleted and receive late is reported.