Fujitsu MB86617A manual Late Packet Decision Range Setting Register a, Bit

LSI Specification MB86617A

7.21. Late Packet Decision Range Setting Register [A]

Late packet decision range setting register [A] is the register that sets Late decision range of source packet to be transmitted by bridge -Ach.

AD

R/W

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

40h

R/W

late range-A

Initial Value

“0000 h ”

BIT

Bit Name

Action

Value

Function

15 - 8

Write in Late packet decision range.

Setting range is 0h to FFh (unit: 125μS).

late range-A

Read/

-

Write

7 - 0

Write in Late packet decision range.

Setting range is 0h to C0h (unit: 16/24.576MHz).

Note)

Late packet decision is performed by comparing the time difference between SPH (Source Packet Header) and CTR (Cycle Time Monitor). -Transmit:

Packet is transmitted normally when calculation result of “SPH” minus “CTR” for source packet transmitted from Bridhe-Ach is within the “late range-A + ‘0000’h”.

If it is out of range, Late packet process is performed. The packet concerned is deleted and transmit late is reported. Set the upper 16 bit of the setting value for transmit offset setting register[A] (14h to 16h).

-Receive:

Received packet is output at the point of “SPH = CTR” when calculation result of “ SPH” minus “ CTR” for source packet received at Bridhe -Ach is within the “late range-A + ‘0000’h” (the value this register is shifted 4 bits to the left).

If it is out of range, Late packet process is performed. The packet concerned is deleted and receive late is reported.

Rev.1.0 55 Fujitsu VLSI