| LSI Specification |
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| MB86617A |
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| BIT | Bit Name |
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| 0 | Indicates that data length of receive packet is same as specified data length in | |
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| 10 | Rx |
| Read |
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| Indicates that data length of receive packet differs to the specified data length in the | |||||
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| 1 | format. | |
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| Clears to ‘0’ by lead of this register. | |
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| 9 | Reserved |
| Read | - | Always indicates ‘0’. | |
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| 0 | Indicates that transmit packet is transmitted normally. | |
| 8 | Tx |
| Read |
| Indicates that transmit packet became Late packet. Delete packet, and not | |
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| 1 | transmit. | |
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| Clears to ‘0’ by lead of this register. | |
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| 0 | Indicates that received packet is normal. | |
| 7 | Rx |
| Read |
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| Indicates that received packet was Late packet. | ||||
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| 1 | Deletes packet, and does not output to TSP | |
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| Clears to ‘0’ by lead of this register. | |
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| 0 | Indicates that 50/60 range of CIP header of received Isochronous packet is ‘0’. | |
| 6 | Rx 56 |
| Read |
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| Indicates that 50/60 range of CIP header of received Isochronous packet is ‘1’ | ||||
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| 1 | ||
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| Clears to ‘0’ by lead of this register. | ||
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| 0 | Indicates that STYPE range of CIP header of received Isochronous packet is | |
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| ‘00000’ or ‘00001’. | ||
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| 5 | Rx stype |
| Read |
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| Indicates that STYPE range of CIP header of received Isochronous packet is other | ||||
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| 1 | than ‘00000’ or ‘00001’. | |
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| Clears to ‘0’ by lead of this regist er. | |
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| BRG FIFO |
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| 0 | Indicates that FIFO on LINK I/F side of | |
| 4 |
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| 1 | Indicates that FIFO on LINK I/F side of | ||||
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| BRG FIFO |
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| 0 | Indicates that FIFO on LINK I/F side of | |
| 3 |
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| 1 | Indicates that FIFO on LINK I/F side of | ||||
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| 0 | Indicates that DBC range of CIP header of received Isochronous packet is normal. | |
| 2 | Rx DBC |
| Read |
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| Indicates that DBC range of CIP header of received Isochronous packet is not | |||||
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| 1 | consecutive. | |
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| Clears to ‘0’ by lead of this register. | |
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Rev.1.0 | 66 | Fujitsu VLSI |