Fujitsu MB86617A LSI Specification MB86617A , , 7.3. instruction-fetch Register

LSI Specification
MB86617A
Rev.1.0 Fujitsu VLSI
31
7.3. instruction-fetch Register
instruction-fetch register is the register that writes in instructions for this LSI, and consists of the instruction code and operand.
Refer to “Chapter 9 Instruction” for each instruction code and operand code.
AD R/W Bit
15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
04h R/W Instruction code operand
Initial Value “00 h” “00 h”
BIT Bit Name Action Value Function
15 - 8 instruction
code Read/ Write - Specify each instruction code.
7 - 0 operand Read/
Write - Specify required operand for each instruction code. Write ‘0’ into all bits for instructions without operand.
Note) Before writing in instruction for this register, read out IPC busy Bit (bit15) of “7.2. flag & status Register”, and confirm that the
IPC busy value is ‘0’.