Instruction-fetch Register | Fujitsu MB86617A instruction

LSI Specification

MB86617A

7.3.instruction-fetch Register

instruction -fetch register is the register that writes in instructions for this LSI, and consists of the instruction code and operand. Refer to “Chapter 9 Instruction” for each instruction code and operand code.

AD		R/W	Bit		Bit		Bit		Bit			Bit	Bit	Bit	Bit	Bit	Bit	Bit		Bit		Bit	Bit	Bit	Bit
AD		R/W	15		14	13			12			11	10	9	8	7	6	5		4		3	2	1	0
			15		14	13			12			11	10	9	8	7	6	5		4		3	2	1	0

04h		R/W							Instruction code											operand

Initial Value										“00 h”											“00 h”


BIT			Bit Name				Action					Value						Function

15 - 8			instruction					Read/			-		Specify each instruction code.
15 - 8				code				Write			-		Specify each instruction code.
				code				Write

7 - 0			operand					Read/			-		Specify required operand for each instruction code.
7 - 0			operand					Write			-		Write ‘0’ into all bits for instructions without operand.
								Write					Write ‘0’ into all bits for instructions without operand.

Note) Before writing in instruction for this register, read out IPC busy Bit (bit15) of “7.2. flag & status Register”, and confirm that the IPC busy value is ‘0’.

Rev.1.0

31

Fujitsu VLSI

Image 36

Fujitsu MB86617A manual Instruction-fetch Register