Contents
Main
LSI Specification MB86617A
Rev.1.0 Fujitsu VLSI
for DTV MB86617A LSI Specification
Contents
iii
Page
Page
Chapter 1 Overview
LSI Specification MB86617A
Chapter 2 Features
Chapter 3 Chip Block
3.1. Block Diagram
<<Normal Operation Mode
<<Asynchronous Transmit FIFO Extended Mode
<<Asynchronous Receive FIFO Extended Mode
3.2. Function of Each Block
<<PHY Layer Control Circuit
<<LINK Layer Control Circuit
<<TSP IC Interface
<<CP IC Interface
Chapter 4 Pin Assignment
LSI Specification MB86617A
9
4.1. Pin Assignment
The following diagram shows the MB86617A pin assignment.
MB86617 FPT-176P-M03
4.2. Corresponding Table of MB86617A Pin
4.3. Outline Drawing of Package
Chapter 5 Pin Function
5.1. IEEE1394 Interface
5.2. Isochronous Interface
Page
5.4. MPU Interface
5.5. Other Pins
5.6. Power/GND Pin
Chapter 6 Internal Register
Page
Page
Page
Page
Page
Chapter 7 Internal Register Function Description
Page
7.1. M ode-control Register
Page
7.2. flag & status Register
Page
LSI Specification MB86617A
7.3. instruction-fetch Register
7.4. interrupt-factor Indicate Register/interrupt-mask Setting Register
7.5. Receive Acknowledge Indicate Register
7.6. A-buffer Data Port Receive/Transmit
7.7. TSP Transmit Information Setting Register [A]
Page
7.8. TSP Transmit Information Setting Register [B]
Page
7.9. Transmit Offset Setting Register [A]
7.10. Transmit Offset Setting Register [B]
7.11. TSP Receive Information Setting Register
Page
Page
Page
Page
7.14. TSP Status Register
Page
7.15. Data Bridge Transmit Information Setting Register 1 [A]
7.16. Data Bridge Transmit Information Setting Register 2 [A]
7.17. Data Bridge Transmit Information Setting Register 3 [B]
7.18. Data Bridge Transmit Information Setting Register 4 [B]
7.19. Data Bridge Receive Information Setting Register
7.20. Transmit Packet Link/Split Setting Register
Page
7.21. Late Packet Decision Range Setting Register [A]
LSI Specification MB86617A
7.22. Late Packet Decision Range Setting Register [B]
7.23. Receive Isochronous Packet Header Indicate Register 1 [A]
7.24. Receive Isochronous Packet Header Indicate Register 2 [A]
7.25. Receive Isochronous Packet Header Indicate Register 3 [B]
7.26. Receive Isochronous Packet Header Indicate Register 4 [B]
LSI Specification MB86617A
7.27. FIFO Reset Setting Register
7.28. Data Bridge Transmit/Receive Status Register [A]
Page
Page
7.29. Data Bridge Transmit/Receive Status Register [B]
Page
Page
7.30. Isochronous Channel Monitor Register
7.31. Cycle-timer-monitor Indicate Register
7.32. Ping Time Monitor Register
7.33. PHY/LINK Register/Address Setting Register
7.34. PHY/LINK Register Access Port
7.35. Revision Indicate Register
7.36. Transmit CGMS/TSCH Indicate Register [A]
7.37. Transmit CGMS/TSCH Indicate Register [B]
7.38. Transmit CGMS/TSCH Indicate Status Register
Page
7.39. Transmit EMI/OE Setting Register
Page
Chapter 8 PHY/INK Register Function Description
LSI Specification MB86617A
8.1. PHY/LINK Register Table
Page
8.2. Physical register #00 (read)
8.3. Physical register #01 (read/write)
8.4. Physical register #02 (read)
8.5. Physical register #03 (read)
8.6. Physical register #04 (read/write)
8.7. Physical register #05 (read/write)
Page
8.8. Physical register #07, 08, 09 (read)
8.9. Physical register #0A, 0B, 0C (read/write)
8.10. Physical register #0D, 0E, 0F (read/write)
8.11. Physical register #10 (read)
8.12. Physical register #11, 12, 13 (read)
LSI Specification MB86617A
8.13. Physical register #14, 15, 16 (read)
<< Description of Eac h Bit
8.14. Physical register #17, 18, 19, 1A, 1B, 1C, 1D, 1E (read/write )
8.15. Link register #00 (read/write)
8.16. Link register #01 (read/write)
Link Register#00 is the register that sets this node to perform as cycle master.
8.17. Link register #02 (read/write)
8.18. Link register #03 (read/write)
Chapter 9 Instruction
9.1. Instruction Code Table
LSI Specification MB86617A
9.2. Description of Each Instruction
<< Start sleep (01 h)
<< Remove sleep (02 h)
<< Asynchronous Receive (03 h)
<< Remove busy mode (04 h)
LSI Specification MB86617A
<< Asynchronous Send (31 h)
<< Data -FIFO init (63h)
Page
Chapter 10 Interrupt
10.1. Interrupt-factor Indicator Register & interrupt-mask Setting Register
10.2. Interrupt
10.3. Description of Interrupt
Page
Page
Chapter 11 Operation
11.1. Initialization
11.2. Self-ID Packet Receiving
Page
LSI Specification MB86617A
<< Flow chart before bus reset completion
LSI Specification MB86617A
<< Flow chart after bus reset completion
LSI Specification MB86617A
11.2.2 Self-ID Packet Receive after Transmitting Ping Packet Ping
<< Flow chart from transmitting of Pig packet to receiving Self-ID packet Ping
LSI Specification MB86617A
<< Flow chart after receiving Self-ID packet
LSI Specification MB86617A
11.3.
Asynchronous Packet Transmitting
<< Flow chart before storing transmitting data into Asynchronous transmit FIFO
LSI Specification MB86617A
<< Flow chart after storing transmitting data into Asynchronous transmit FIFO
11.4. Asynchronous Packet Receiving
LSI Specification MB86617A
<< Flow chart for received data before storing in Asynchronous receive FIFO
LSI Specification MB86617A
<< Flow chart for received data after storing in Asynchronous receive FIFO
11.5. Isochronous Packet Transmitting
Page
Page
11.6. Isochronous Packet Receiving
Page
Chapter 12 System Configuration
12.1. Recommended Connection for 1934 Port (for one port)
12.2
12.3. Recommended Connection for Build-in PLL Loop Filter
FIL
RF
12.4. Configuration of Feedback Circuit at Crystal Oscillator