Fujitsu MB86617A manual Data Bridge Receive Information Setting Register

LSI Specification MB86617A

7.19. Data Bridge Receive Information Setting Register

Data bridge receive information register performs the setting of receive packet.

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R/W

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

3Ch

R/ョ

Rx

Rx

Rx channel-B

Rx

Rx

Rx channel-A

start

end

start

end

-B

-B

-A

-A

Initial Value

‘0’

‘0’

“00 h”

‘0’

‘0’

“00 h”

BIT

Bit Name

Action

Value

Function

0

Automatically clears when receive process is executed by bridge- Bch after setting

Read/

at ‘1’.

15

Rx start -B

Write

1

Executes receive process by bridge -Bch.

0

Automatically clears when receive process is stopped by bridge -Bch after setting at

Read/

‘1’.

14

Rx end-B

Write

1

Stops receive process by bridge -Bch.

13~8

Rx channel-B

Read/

-

Write in Isochronous packet channel to be received by bridge-Bch.

Write

(MSB: bit8, LSB: bit3)

0

Automatically clears when receive process is executed by bridge- Ach after setting

Read/

at ‘1’.

7

Rx start -A

Write

1

Starts receive process by bridge -Ach.

0

Automatically clears when receive process is stopped by bridge -Ach after setting at

Read/

‘1’.

6

Rx end-A

Write

1

Stops receive process by bridge -Ach.

5 - 0

Rx-channel-A

Read/

-

Write in Isochronous packet channel to be received by bridge-Ach

Write

(MSB: bit5, LSB: bit0)

Rev.1.0 52 Fujitsu VLSI