Fujitsu MB86617A manual Buffer Data Port Receive/Transmit

LSI Specification MB86617A

7.6. A-buffer Data Port Receive/Transmit

This integrated register is the buffer access port for both ASYNC receive specific buffer and ASYNC transmit specific one. Read data is able to be read out IEEE1394 packet data in the order received. (MSB: 1ST read)

Write data is transmitted as IEEE1394 packet data in the order written in. (MSB: 1ST write)

AD

R/W

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R

ASYNC Receive Specific Buffer Data

0Ch

W

ASYNC Transmit Specific Buffer Data

Initial Value

Undefined

BIT

Bit Name

Action

Value

Function

ASYNC Receive

Read out port of Asynchronous receive specific buffer.

Specific Buffer

Read

-

(MSB: bit15, LSB: bit0)

Data

15 - 0

ASYNC Transmit

Write

-

Write in port of Asynchronous transmit specific buffer.

Specific Buffer

(MSB: bit15, LSB: bit0)

Data

Rev.1.0 34 Fujitsu VLSI