Fujitsu MB86617A manual 28h

LSI Specification MB86617A

7.13.Receive DSS Packet Header Indicate Register [B]/Transmit DSS Packet Header Setting Register [B]

Receiv e DSS packet header indicate register [B] indicates DSS packet header range of DSS packet received by bridge-Bch. Transmit DSS packet header setting register [B] sets DSS packet header range of DSS packet received by bridge-Bch.

AD

R/W

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R

Rx-SI

Rx-System clock count-B (high)

F-B

28h

Tx-SIF

W

T x-System clock count-B (high)

-B

R

Rx-maximum bit rate-B (low)

Rx-E

reserved

F-B

2Ah

W

T x-maximum bit rate-B (low)

Tx-E

reserved

F-B

R

reserved

2Ch

W

reserved

R

reserved

2Eh

W

reserved

R

reserved

30h

W

reserved

Initial Value

“0000 h ”

BIT	Bit Name	Action	Value	Function
	Rx-SIF-B	Read	-	Indicates SIF range of receive DSS packet header.
15 (28h)
	T x-SIF-B	Write	-	Write in SIF range of transmit DSS packet header.
	Rx-System	Read	-	Indicate System clock count range of receive DSS packet header.
14 - 0 (28h)	clock count-B			(MSB: 28h-bit14, LSB: 2Ah-bit8)
15 - 8(2Ah)
	T x-System	Write	-	Write in System clock count range of transmit DSS packet header.
	clock count-B			(MSB: 28h-bit14, LSB: 2Ah-bit8)
	Rx-EF-B	Read	-	Indicates EF range of received DSS packet header.
7(2Ah)
	Tx-EF-B	Write	-	Write in EF range of transmit DSS packet header.
6 - 0 (2Ah)		Read	-	Indicates reserved range of receive DSS packet header.
7 - 0 (2Ch)	reserved
15 - 0 (2Eh)
15 - 0 (30h)		Write	-	Write in reserved range of transmit DSS packet header.

Rev.1.0 45 Fujitsu VLSI