LSI Specification
MB86617A
Rev.1.0 Fujitsu VLSI
45
Receive DSS packet header indicate register [B] indicates DSS packet header range of DSS packet received by bridge -Bch.
Transmit DSS packet header setting register [B] sets DSS packet header range of DSS packet received by bridge-Bch.
AD R/W Bit
15 Bit
14 Bit
13 Bit
12 Bit
11 Bit
10 Bit
9 Bit
8 Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
R Rx-SI
F-B Rx-System clock count-B (high)
28h
W Tx-SIF
-B Tx-System clock count-B (high)
R Rx-maximum bit rate-B (low) Rx-E
F-B reserved
2Ah
W Tx-maximum bit rate-B (low) Tx-E
F-B reserved
R reserved
2Ch
W reserved
R reserved
2Eh
W reserved
R reserved
30h
W reserved
Initial Value “0000 h”
BIT Bit Name Action Value Function
Rx-SIF-B Read - Indicates SIF range of receive DSS packet header.
15 (28h)
Tx-SIF-B Write - Write in SIF range of transmit DSS packet header.
Rx-System
clock count-B Read - Indicate System clock count range of receive DSS packet header.
(MSB: 28h-bit14, LSB: 2Ah-bit8)
14 - 0 (28h)
15 - 8(2Ah) Tx-System
clock count-B Write - Write in System clock count range of transmit DSS packet header.
(MSB: 28h-bit14, LSB: 2Ah-bit8)
Rx-EF-B Read - Indicates EF range of received DSS packet header.
7(2Ah)
Tx-EF-B Write - Write in EF range of transmit DSS packet header.
Read - Indicates reserved range of receive DSS packet header.
6 - 0 (2Ah)
7 - 0 (2Ch)
15 - 0 (2Eh)
15 - 0 (30h)
reserved
Write - Write in reserved range of transmit DSS packet header.