Fujitsu MB86617A 7.24. Receive Isochronous Packet Header Indicate Register 2 [A]

LSI Specification
MB86617A
Rev.1.0 Fujitsu VLSI
58
7.24. Receive Isochronous Packet Header Indicate Register 2 [A]
Receive Isochronous packet header indicate register 2 [A] is the register that indicates Isochronous packet CIP header information received
by bridge-Ach.
AD R/W Bit
15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
46h R - - - - Rx FMT-A Rx
56-A Rx STYPE-A
Initial Value ‘0’ ‘0’ ‘0’ ‘0’ “3F” ‘0’ “00 h”
BIT Bit Name Action Value Function
15 - 12 reserved Read - Always indicate ‘0’.
11 - 6 Rx FMT-A Read - Indicate FMT range of receive Isochronous packet CIP header.
(MSB: bit11, LSB: bit6)
5 Rx 56-A Read -
Indicates 50/60 range of receive Isochronous packet CIP header when receiving
DV.
Indicates TSF range of receive Isochronous packet CIP header when receiving
MPEG2-TS or DSS.
4 - 0 Rx STYPE-A Read - Indicate STYPE range of CIP header of receive Isochronous packet.
(MSB: bit4, LSB: bit0)