LSI Specification | MB86617A |
7.24. Receive Isochronous Packet Header Indicate Register 2 [A]
Receive Isochronous packet header indicate register 2 [A] is the register that indicates Isochronous packet CIP header information received by
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| R/W |
| Bit |
| Bit |
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| Bit | Bit |
| Bit | Bit |
| Bit |
| Bit | Bit | Bit |
| Bit | Bit | Bit | Bit | Bit | |||
| 15 |
| 14 |
| 13 |
| 12 |
| 11 | 10 | 9 |
| 8 |
| 7 | 6 | 5 |
| 4 | 3 | 2 | 1 | 0 |
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46h |
| R | - |
| - |
| - |
| - |
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| Rx FMT |
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| Rx |
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| Rx |
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Initial Value |
| ‘0’ |
| ‘0’ |
| ‘0’ |
| ‘0’ |
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| “3F” |
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| ‘0’ |
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| BIT |
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| Action |
| Value |
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| Function |
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| 15 - 12 |
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| reserved |
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| Read |
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| Always indicate‘0’. |
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| 11 - 6 |
| Rx FMT |
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| Read |
| - |
| Indicate FMT range of receive Isochronous packet CIP header. |
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| (MSB: bit11, LSB: bit6) |
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| Indicates 50/60 range of receive Isochronous packet CIP header when receiving | ||||||||||||||
| 5 |
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| Rx |
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| Read |
| - |
| DV. |
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| Indicates TSF range of receive Isochronous packet CIP header when receiving |
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| 4 - 0 |
| Rx |
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| Read |
| - |
| Indicate STYPE range of CIP header of receive Isochronous packet. |
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| (MSB: bit4, LSB: bit0) |
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Rev.1.0 | 58 | Fujitsu VLSI |