LSI Specification | MB86617A |
<Host>
START
Set necessary data to registers such as Bridg and TSPIF(Note).
Input the source packet data and clock
into TSPIF port.
Read Transmit late occurred (INT32)
interrupt.
<Device>
Set value to registers such as Bridge and
TSPIF.
Store source packet in FIFO at TSPIF.
Transmit source packet to CP LSI.
Receive processed source packet from
CP LSI and store it in FIFO at Bridge.
Isocycle |
No |
Yes |
Arbitration procedure |
|
Arbitration result | Lost |
| |
Won |
|
Transmit Late evaluation
Transmit Late
Yes
Report Transmit late occurred (INT32) interrupt(assert XINT).
Discard source packet and transmit
empty packet.
Connect source packet according to
register setting and transmit.
END
Figure 11.5 Flow example for transmitting Isochronous packet
Rev.1.0 | 126 | Fujitsu VLSI |
