Fujitsu MB86617A specification

LSI Specification

MB86617A

7.23. Receiv e Isochronous Packet Header Indicate Register 1 [A]

Receive Isochronous packet header indicate register 1 [A] is the register that indicates Isochronous packet header information received by bridge-Ach.

AD		R/W		Bit		Bit	Bit			Bit		Bit		Bit	Bit	Bit		Bit	Bit	Bit		Bit		Bit	Bit	Bit	Bit
AD		R/W	15			14	13			12		11	10		9	8		7	6	5		4		3	2	1	0
			15			14	13			12		11	10		9	8		7	6	5		4		3	2	1	0

44h		R	-			-	-			-		-	-		-	Rx EMI-A			Rx					Rx SID-A
44h		R	-			-	-			-		-	-		-	Rx EMI-A			o/e-A					Rx SID-A
																			o/e-A

Initial Value				‘0’		‘0’	‘0’			‘0’		‘0’		‘0’	‘0’	“00 b”			‘0’					“00 h”


		BIT			Bit Name				Action			Value								Function

	15 - 9				reserved				Read			-		Always indicate‘0’.

	8 - 7			Rx EMI-A					Read			-		Indicate EMI range of receive Isochronous packet header.
	8 - 7			Rx EMI-A					Read			-		(MSB: bit8, LSB: bit7)
														(MSB: bit8, LSB: bit7)

	6				Rx o/e-A				Read			-		Indicates odd/even range of receive Isochronous packet header.

	5 - 0				Rx SID-A				Read			-		Indicate SI range of CIP header of receive Isochronous packet.
	5 - 0				Rx SID-A				Read			-		(MSB: bit8, LSB: bit3)
														(MSB: bit8, LSB: bit3)

Rev.1.0

57

Fujitsu VLSI

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Fujitsu MB86617A manual Receiv e Isochronous Packet Header Indicate Register 1 a