Fujitsu MB86617A 7.23. Receive Isochronous Packet Header Indicate Register 1 [A]

LSI Specification
MB86617A
Rev.1.0 Fujitsu VLSI
57
7.23. Receive Isochronous Packet Header Indicate Register 1 [A]
Receive Isochronous packet header indicate register 1 [A] is the register that indicates Isochronous packet header information received by
bridge-Ach.
AD R/W Bit
15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
44h R - - - - - - - Rx EMI-A Rx
o/e-A Rx SID-A
Initial Value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ “00 b” ‘0’ “00 h”
BIT Bit Name Action Value Function
15 - 9 reserved Read - Always indicate ‘0’.
8 - 7 Rx EMI-A Read - Indicate EMI range of receive Isochronous packet header.
(MSB: bit8, LSB: bit7)
6 Rx o/e-A Read - Indicates odd/even range of receive Isochronous packet header.
5 - 0 Rx SID-A Read - Indicate SI range of CIP header of receive Isochronous packet.
(MSB: bit8, LSB: bit3)