LSI Specification
MB86617A
Rev.1.0 Fujitsu VLSI
65
7.29. Data Bridge Transmit/Receive Status Register [B]
Data bridge transmit/receive status register [B] indicates status of packet transmitted/received by bridge-Bch.
AD R/W Bit
15 Bit
14 Bit
13 Bit
12 Bit
11 Bit
10 Bit
9 Bit
8 Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
50h R Tx
busy-
B
Rx
busy-
B
Rx
1STP-
B
Rx
EMI
chg-B
Rx o/e
chg-B
Rx
dlen
err-B - Tx
late-B Rx
late-B Rx 56
err-B
Rx
stype
err-B
BRG
FIFO
full-B
BRG
FIFO
emp-
B
Rx
DBC
err-B
Rx
CIP
err-B
Rx
FMT
err-B
Initial Value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘1’ ‘0’ ‘0’ ‘0’
BIT Bit Name Action Value Function
0 Indicates that bridge-Bch is not in the process of transmit.
Indicates ‘0’ when Tx end-B (12h-bit14) is set at ‘1’ and transmit process is
stopped.
15 Tx busy-B Read
1 Indicates that bridge-Bch is in the process of transmit.
Indicates ‘1’ when Tx start-B (12h-bit15) is set at ‘1’ and transmit process is
started.
0 Indicates that bridge-Bch is not in the process of receive.
Indicates ‘0’ when Rx end-B (3Ch-bit14) is set at ‘1’ and receive process is
stopped.
14 Rx busy-B Read
1 Indicates that bridge-Bch is in the process of receive.
Indicates ‘1’ when Rx start-B (3Ch -bit15) is set at ‘1’ and receive process is
started.
0 Indicates that received Isochronous packet after starting receive process is not the
first receive packet.
13 Rx 1STP-B Read
1 Indicates that the first Isochronous packet is received after starting receive process.
Clears to ‘0’ by lead of this register.
0 Indicates that EMI information of receive Isochronous packet header is not
changed.
12 Rx EMI
chg-B Read
1 Indicates that EMI information of receive Isochronous packet header has changed
from just former EMI information of packet received by Isochronous-cycle.
Clears to ‘0’ by lead of this register.
0 Indicates that odd/even information of receive Isochronous packet header is not
changed.
11 Rx o/e chg-B Read
1
Indicates that odd/even information of receive Isochronous packet header has
changed from just former odd/even information of packet received by
Isochronous-cycle.
Clears to ‘0’ by lead of this register.