LSI Specification

 

 

 

 

 

 

 

 

 

 

MB86617A

 

10.1. Interrupt-factor Indicator Register & interrupt-mask Setting Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AD

R/

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

 

Bit

Bit

Bit

Bit

Bit

 

15

14

13

12

11

10

9

8

7

6

5

 

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R

INT

INT

INT

INT

INT

INT

INT

INT

INT

INT

INT

 

INT

INT

INT

INT

INT

 

 

1

2

3

4

5

6

7

8

9

10

11

 

12

13

14

15

16

 

06h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

W

 

 

 

 

 

 

 

interrupt-mask

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R

INT

INT

INT

INT

INT

INT

INT

INT

INT

INT

INT

 

INT

INT

INT

INT

INT

 

 

17

18

19

20

21

22

23

24

25

26

27

 

28

29

30

31

32

 

08h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

W

 

 

 

 

 

 

 

Interrupt-mask

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Intial Value

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

 

‘0’

‘0’

‘0’

‘0’

‘0’

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

>interrupt-factor Indicate Register

This register indicate the interrupt content reported by this device. Do not indicate the interrupt code specified MASK. Do not reflect its code to XINT terminal either.

>interrupt-mask setting register

This register masks the interrupt reported by this device. Do not report the interrupt if ‘1’ is set for Bit corresponding to interrupt factor.

Rev.1.0

107

Fujitsu VLSI

Page 112
Image 112
Fujitsu MB86617A manual Intial Value ‘0’