LSI Specification

MB86617A

11.2.1Self-ID Packet Receive at Bus Reset Process

This section explains the receiving process of Self-ID packet.

The MB86617A device is capable of receiving self-ID packets that each mode transmit in the self-identity stage of bus reset process. When ‘1’ is written to the s-ID store bit of mode- control register (refer to 7.1), the self-ID packet in the bus reset process can be received and the data removing the logical inverse section is stored in the Asynchronous receive- FIFO and Asynchronous transmit -FIFO (512 bytes maxixum). When the number of total data exceeds 512 bytes, the overflown data are discarded.

Bus reset force-clears FIFO for Asynchronous receiving and FIFO for Asynchronous transmitting to store Self-ID packet.

Rev.1.0

115

Fujitsu VLSI

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Fujitsu MB86617A manual Self-ID Packet Receive at Bus Reset Process