Fujitsu MB86617A manual TSP Status Register, Tsp, Fifo

LSI Specification MB86617A

7.14. TSP Status Register

TSP status register indicates status of TSP -IC I/F.

AD

R/W

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

32h

R

CG

TS

no

TSP

TSP

Tx-len

-

-

CG

TS

no

TSP

TSP

Tx-len

-

-

FIFOf

FIFO

gth-err-

FIFO

FIFO

gth-err-

chg-B

chg-B

47h-B

chg-A

chg-A

47h-A

ull-B

emp-B

B

full-A

emp-A

A

Initial Value

‘0’

‘0’

‘0’

‘0’

‘1’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘1’

‘0’

‘0’

‘0’

BIT

Bit Name

Action

Value

Function

0

Indicates that CGMS information input from port B of TSP IC I/F is not changed.

15

CG chg-B

Read

Indicates that CGMS information corresponding to TSCH classification ID of same

1

type input from port B of TSP IC I/F is changed.

Clears to ‘0’ by lead of this register.

0

Indicates that TS classification ID input from port B of TSP IC I/F is not changed.

14

TS chg-B

Read

Indicates that TSCH classification ID input from port B of TSP IC I/F is not

1

consistent with TSCH classification ID (10h- bit12 to 7 set TS-ID- A or 12h- bit12 to

7 set TS-ID-B) to be stored to FIFO.

Clears to ‘0’ by lead of this register.

0

Indicates that synchronization byte of received MPEG2-TS input from CP -IC by

bridge-Bch is 47h

13

no 47h -B

Read

Indicates that synchronization byte of received MPEG2 -TS input from CP -IC by

1

bridge-Bch is not 47h

Clears to ‘0’ by lead of this register.

TSP FIFO

0

Indicates that FIFO on TSP IC I/F side of bridge-Bch is not full.

12

Read

full-B

1

Indicates that FIFO on TSP IC I/F side of bridge-Bch is full.

TSP FIFO

0

Indicates that FIFO on TSP IC I/F side of bridge-Bch is not empty.

11

Read

emp-B

1

Indicates that FIFO on TSP IC I/F side of bridge -Bch is empty.

0

Indicates that transmit data length input from TSP IC I/F is normal.

T x-length-err -

10

Read

Indicates that transmit data length input from TSP IC I/F is not consistent with

B

1

specified format data length.

Deletes transmit data without writing into FIFO.

Clears to ‘0’ by lead of this register.

Rev.1.0 46 Fujitsu VLSI