LSI Specification |
| MB86617A | |||
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| IERRA |
| O | Output pin for noticing error of receive data (on port A) |
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| ‘H’ active signal |
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| IERRB |
| O | Output pin for noticing error of receive data (on port B) |
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| ‘H’ active signal |
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| DSSCLKA |
| I | Clock input pin for DSS data (27MHz) |
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| DSSCLKB |
| I | Clock input pin for DSS data (27MHz) |
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Rev.1.0 | 15 | Fujitsu VLSI |
