LSI Specification | MB86617A |
7.34. PHY/LINK Register Access Port
PHY/LINK register access port is the port to access PHY/LINK register indirectly. PHY/LINK register indicated with address set by PHY/LINK register/address setting register can be accessed from this port.
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| R/W | Bit | Bit |
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| Bit | Bit |
| Bit | Bit | Bit |
| Bit |
| Bit | Bit |
| Bit | Bit | Bit |
| Bit | Bit | ||
| 15 | 14 | 13 |
| 12 |
| 11 | 10 |
| 9 | 8 |
| 7 |
| 6 | 5 |
| 4 | 3 | 2 |
| 1 | 0 | ||||
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62h |
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Initial Value |
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| “0000 h” |
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BIT |
| Bit Name |
| Action |
| Value |
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| Function |
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| Read |
| - |
| Indicates | PHY/LINK | register | contents defined by | address | set | by PHY/LINK | ||||||||||
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| register/address setting register. (MSB: 15, LSB: 0) |
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15 - 0 |
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| Write |
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| Executes write in the process of register defined by this address set by PHY/LINK | |||||||||||||||||||||
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| register/address setting register. (MSB: 15, LSB: 0) |
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Rev.1.0 | 72 | Fujitsu VLSI |