LSI Specification | MB86617A |
7.25.Receive Isochronous Packet Header Indicate Register 3 [B]
7.26.Receive Isochronous Packet Header Indicate Register 4 [B]
7.27.FIFO Reset Setting Register
7.28.Data Bridge Transmit/Receive Status Register [A]
7.29.Data Bridge Transmit/Receive Status Register [B]
7.30.Isochronous channel monitor Register
7.31.
7.32.Ping time monitor Register
7.33.PHY/LINK Register/Address Setting Register
7.34.PHY/LINK Register/Access Port
7.35.Revision Indicate Register
7.36.Transmit CGMS/TSCH Indicate Register [A]
7.37.Transmit CGMS/TSCH Indicate Register [B]
7.38.Transmit CGMS/TSCH Indicate Status Register
7.39.Transmit EMI/OE Setting Register
Rev.1.0 | 26 | Fujitsu VLSI |
