Fujitsu MB86617A manual Asynchronous Receive Fifo Extended Mode

LSI Specification MB86617A

<Asynchronous Receive FIFO Extended Mode

	Asynch Transmit
	Exclusive FIFO
	(256 byte)
Host	Asynch Transmit
	Packet Process
Interface	Asynch Transmit
	Packet Process
	Asynch Transmit
	Exclusive FIFO
	(256 byte)

			PHY/
			LINK
FIFO		FIFO	Layer
			Control
(2KByte)		(2KByte)
			Circuit
TSP IC		Data
Interface		Bridge
FIFO	CP IC	FIFO
(2KByte)		(2KByte)
	Interface
	Fig.3.1.3 Block Diagram - Asynchronous Receive FIFO Extended Mode -

1394 Interface (Port 0)

1394 Interface (Port 1)

1394 Interface (Port 2)

TPA0

XTPA0

TPB0

XTPB0

TPBIAS0

TPA1

XTPA1

TPB1

XTPB1

TPBIAS1

TPA2

XTPA2

TPB2

XTPB2

TPBIAS2

Rev.1.0 6 Fujitsu VLSI