Fujitsu MB86617A 7.5. Receive Acknowledge Indicate Register

LSI Specification
MB86617A
Rev.1.0 Fujitsu VLSI
33
7.5. Receive Acknowledge Indicate Register
Receive Acknowledge indicate register is the register that indicates received Acknowledge packet addressed to itself.
Read out this register after interrupt report of “Asynchronous packet send”.
AD R/W Bit
15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0Ah R - - - - - - - - Receive ack-code Receive ack-parity
Initial Value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ “0 h” “0 h”
BIT Bit Name Action Value Function
15 - 8 reserved Read - Always indicate ‘0’.
7 - 4 Receive Acknowledge-co
de Read - Indicate code of received Acknowledge packet addressed to it.
(MSB: bit7, LSB: bit5)
3 - 0 Receive
Acknowledge-par
ity Read - Indicate parity of received Acknowledge packet addressed to it.
(MSB: bit3, LSB: bit0)
Note) In case of not receiving Acknowledge within specified time, this register indicates “00h” and reports interrupt of “Acknowledge
missing”.