Fujitsu MB86617A manual Transmit Offset Setting Register a

LSI Specification MB86617A

7.9. Transmit Offset Setting Register [A]

Transmit offset setting register [A] is the register that sets offset value added to cycle-time-monitor value. Its aim is to generate source packet header (Time -stamp) added to transmit packet processed by bridge -Ach. (Max. 32 ms)

Time-stamp value is generated on the basis of cycle-time-monitor value at input of first byte of source packet from TSP -IC.

AD

R/W

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

14h

R/W

reserved

transmit-offset-A (high)

16h

R/W

transmit-offset-A (low)

Initial Value

“0000 h”

BIT

Bit Name

Action

Value

Function

Read

-

Always indicate ‘0’.

15 - 4 (high)

reserved

Write

-

Always write in ‘0’.

3 - 0 (high)

Set value to be added to cycle-count range of cycle-time-monitor.

15 - 12 (low)

Setting range is 0h to FFh. (unit=125μS).

transmit-offset

Read/

-

-A

Write

11 - 0

Set value to be added to cycle-offset range of cycle -time-monitor.

Setting range is 0h to C00h. (unit=1/24.576 MHz).

Rev.1.0 39 Fujitsu VLSI