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Motorola MVME187 manual Disk/Tape Controller Default Conﬁgurations, $Xxxxxxxx

Models: MVME187

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Disk/Tape Controller Default Conﬁgurations

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Disk/Tape Controller Data

Disk/Tape Controller Default Conﬁgurations

Note SCSI Common Command Set (CCS) devices are only the ones tested by Motorola Computer Group.

RISC Single Board Computers -- 7 Devices

Controller LUN	Address	Device LUN	Device Type

0	$XXXXXXXX	00	SCSI Common Command Set
		10	(CCS), which may be any of these:
		20	- Fixed direct access
		30	- Removable ßexible direct access
		40	(TEAC style)
		50	- CD-ROM
		60	- Sequential access

MVME320 -- 4 Devices

Controller LUN	Address	Device LUN	Device Type

11	$FFFFB000	0	Winchester hard drive
		1	Winchester hard drive
		2	5-1/4" DS/DD 96 TPI ßoppy drive
12	$FFFFAC00	2	5-1/4" DS/DD 96 TPI ßoppy drive
		3	5-1/4" DS/DD 96 TPI ßoppy drive

MVME323 -- 4 Devices

Controller LUN	Address	Device LUN	Device Type

8	$FFFFA000	0	ESDI Winchester hard drive
		1	ESDI Winchester hard drive
		2	ESDI Winchester hard drive
9	$FFFFA200	2	ESDI Winchester hard drive
		3	ESDI Winchester hard drive

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Motorola MVME187 manual Disk/Tape Controller Default Conﬁgurations, $Xxxxxxxx

Contents

MVME187 RISC Single Board Computer Installation Guide MVME187IG/D4Restricted Rights Legend Preface Safety Summary Safety Depends On You Do Not Service or Adjust AloneUse Caution When Exposing or Handling the CRT Dangerous Procedure WarningsThis equipment generates, uses, and can radiate electro Page Contents Front Panel Switches and LEDs Data Bus Structure Local Bus Arbitration M88000 MPU EPROM Programmable EPROM FeaturesStatic RAM Optional SRAM Battery Backup Onboard DRAM Battery Backed Up RAM and Clock VMEbus Interface I/O InterfacesJumper Settings Optional Jumper Settings Installing the Hardware Installing the MVME187 in the ChassisCompleting the Installation 3-24 Starting the System Powering Up the System 3-25 Initializing the Real-Time ClockBooting and Restarting 187Bug 4-5 Starting Up 187Bug 4-6 Autoboot Autoboot Sequence 4-6 ROMboot ROMboot Sequence 4-7 Network BootNetwork Boot Sequence 4-8 Restarting the System Reset Abort Break BO Bootstrap Operating System 4-15 BH Bootstrap and HaltMultiprocessor Address Register MPAR 4-22 MPCR Powerup Sequence 187Bug Diagnostic Test Groups 4-27 This Chapter CoversThe 187Bug Debugger Command Set 5-15 This Appendix Covers A-1 MPCR Status CodesSignal Adaptations E-4 Sample ConÞgurations E-4 Proper Grounding E-7 List of Figures MVME187 General Block DiagramUsing MVME712A/AM and MVME712B Typical Transition Module Peripheral Port ConnectorsList of Tables 1Introduction to the MVME187 Installation Guide This Chapter CoversAbout this Manual Signal Name Conventions Terminology, Conventions, and Deﬁnitions Used in this ManualData and Address Parameter Numeric Formats Assertion and Negation Conventions Data and Address Size DeﬁnitionsBig-Endian Byte Ordering Control and Status Bit Deﬁnitions True/False Bit State DeﬁnitionsBit Value Descriptions The bit can be set and cleared under softwareRelated Documentation Document Set for MVME187-0xx BoardAdditional Manuals for this Board Other Applicable Motorola PublicationsAlso available but not included in the set Non-Motorola Peripheral Controllers Publications Bundle Introduction to the MVME187 Installation Guide Data SheetMC68230 Parallel Interface Timer PI/T Data Sheet Part NumberApplicable Non-Motorola Publications ANSI/IEEE StdData, IEC 821 BUS Sheet, order numberIntroduction to the MVME187 Installation Guide 1-10Board Level Hardware Description General DescriptionThis Chapter Covers Onboard Memory Mezzanine Module SCSI Mass Storage InterfaceSerial Ports Parallel Printer PortEthernet Transceiver Interface Features 187Bug FirmwareFour 32-bit tick timers for periodic interrupts Watchdog timer Speciﬁcations Conformance to RequirementsTable 2-1. MVME187 General Speciﬁcations Connectors Figure 2-1. MVME187 General Block DiagramBoard Level Overview AdaptersTransition Modules ASICsVMEchip2 ASIC Table 2-2. Bus TransfersPCCchip2 ASIC Functional Description MEMC040 Memory Controller ASICMCECC Memory Controller ASIC Front Panel Switches and LEDs Table 2-3. Front Panel SwitchesTable 2-4. Front Panel LEDs Data Bus Structure M88000 MPULocal Bus Arbitration Programmable EPROM Features EPROMStatic RAM Optional SRAM Battery Backup Onboard DRAM Stacking Mezzanines DRAM Programming ConsiderationsBattery Backed Up RAM and Clock VMEbus Interface I/O InterfacesSerial Port Interface Serial Interface Programming Considerations Parallel Port Interface Ethernet Interface Buffer Overruns SCSI InterfaceSCSI Termination Programmable Tick Timers Watchdog TimerLocal Bus Timeout Local ResourcesMemory Maps Local Bus Memory MapNormal Address Range Devices Table 2-5. Local Bus Memory Map Table 2-6. Local I/O Devices Memory Map Table 2-6. Local I/O Devices Memory Map Continued VMEbus Accesses to the Local Bus VMEbus Memory MapVMEbus Short I/O Memory Map Hardware Preparation and Installation Unpacking the EquipmentThis Chapter Covers Overview of Startup Procedure Table 3-1. Startup OverviewTable 3-1. Startup Overview Continued obtain the Single BoardComputer SCSI Software UserÕs ManualTable 3-1. Startup Overview Continued pageobtain the Debugging Modifying Conﬁguration before Installation Preparing the HardwareOption Modiﬁcation Figure 3-1. MVME187 Switches, Headers, Connectors, Fuses, and LEDs MVMEJumper Settings Checking the 187Bug EPROMsEPROM Location EPROM OrientationOptional Jumper Settings General Purpose Software Readable Header J1Reserved/DeÞned Bits Table 3-3. Factory Settings for J1 General Purpose Readable Jumpers Table 3-2. J1 Bit DescriptionsGPI0 - GPI3 GPI4 - GPI7Table 3-4. Settings for J2 System Controller Header System Controller Header J2System Optional SRAM Backup Power Source Select Header J6 Serial Port 4 Clock Conﬁguration Select Headers J7 and J8Table 3-5. Settings for Optional J6 SRAM Backup Power Source Select HeaderTable 3-6. Settings for J7 and J8 Serial Port 4 Clock Conﬁguration Select HeadersSerial Port clockPreparing the MVME187 for Installation Table 3-7. MVME187 Preparation ProcedureTable 3-8. Chassis Preparation/Slot Selection Procedure Preparing the System ChassisInstalling the Hardware Installing the MVME187 in the ChassisTable 3-9. MVME187 Installation Procedure Transition Modules and Adapter Boards Overview Installing the Hardware3-17 Figure 3-2. Typical Internal SCSI and Serial Port Connections Hardware Preparation and Installation3-18 Equipment Connections Table 3-10. Peripheral ConnectionsSome connection diagrams are in the Single Board Computer External SCSI drivesInstalling Transition Modules and Adapter Boards Connecting PeripheralsTable 3-11. Transition Module and Adapter Board Installation Overview Table 3-12. Peripheral Connection Procedures parity disabled no paritybaud rate 9600 baud default baud rate of MVME187 ports at powerupFigure 3-3. Using MVME712A/AM and MVME712B Figure 3-4. Typical Transition Module Peripheral Port Connectors MVME712A To J10 onCompleting the Installation Table 3-13. Installation Completion ProcedureStarting the System Table 3-14. System Startup OverviewPowering Up the System Initializing the Real-Time ClockExamining and/or Changing Environmental Parameters Board ModeTable 3-15. RTC Initialization Procedure Programming the PCCchip2 and VMEchip2SET MMddyyhhmm+/-CALC 187-BugSET 0522961037 ReturnBackplane Power Connections Global Bus TimeoutSystem Considerations Memory Address RangesMultiple Module Cage Conﬁguration GCSR Location Monitor RegisterEthernet LAN +12 Vdc Fuse SCSI Bus Termination Storage and the Real-Time Clock187-Bugps Return Hardware Preparation and Installation 3-30Debugger General Information Introduction to MVME187BugOverview of M88000 Firmware This Chapter CoversCommand Facilities Description of 187BugTrap #496 Routines Debugger or Diagnostic Directories Keyboard ControlComparison with M68000-Based Firmware 187Bug ImplementationBooting and Restarting 187Bug Memory RequirementsAutoboot Autoboot SequenceStarting Up 187Bug ROMboot ROMboot SequenceNetwork Boot Network Boot SequenceRestarting the System Reset During COLD resetDuring WARM reset AbortAbort Sequence BreakBreak Sequence SYSFAIL* Assertion/NegationMPU Clock Speed Calculation Disk I/O Support Disk Support FacilitiesParameter Tables Supported ControllersBlocks Versus Sectors Device Probe FunctionDisk I/O via 187Bug Commands BO Bootstrap Operating SystemIOI Input/Output Inquiry IOP Physical I/O to DiskBH Bootstrap and Halt Controller Command PacketsDisk I/O via 187Bug System Calls Default 187Bug Controller and Device Parameters Disk I/O Error Codes sourceNetwork I/O Support Intel 82596 LAN Coprocessor Ethernet DriverUDP/IP Protocol Modules BOOTP Protocol Module Network Boot Control ModuleRARP/ARP Protocol Modules TFTP Protocol ModuleNetwork I/O Error Codes Multiprocessor SupportMultiprocessor Control Register MPCR Method MPCR Powerup Sequence MPCR Status CodesMultiprocessor Address Register MPAR 3. As the initialization proceeds, the execution path comes to the prompt routine Global Control and Status Register GCSR Method Diagnostic Facilities Table 4-1. Diagnostic Monitor Commands/PreﬁxesTable 4-2. Diagnostic Utilities Table 4-1. Diagnostic Monitor Commands/PreﬁxesCommand Command187Bug Diagnostic Test Groups Table 4-3. Diagnostic Test GroupsDebugger General Information 4-28Using the 187Bug Debugger Entering Debugger Command LinesTerminal Input/Output Control This Chapter CoversUsing the 187Bug Debugger Debugger Command Syntax Syntactic Variables Expression as a ParameterAddress as a Parameter Address Formats Port Numbers Offset RegistersEntering and Debugging Programs Creating a Program with the Assembler/DisassemblerDownloading an S-Record Object File Calling System Utilities from User Programs Read the Program from DiskPreserving the Debugger Operating Environment 187Bug Vector Table and WorkspaceFloating Point Support Hardware FunctionsException Vectors Used by 187Bug CPU/MPU Registers1. The sign field is the first field and is a binary field Single Precision Real Double Precision Real2 hex digits. Bias = $7F 3 hex digits. Bias = $3FFScientiﬁc Notation The 187Bug Debugger Command Set Table 5-1. Debugger CommandsAS addr BC range del addr B H WTable 5-1. Debugger Commands Continued HE commandDMA range del addr del vdir del am del blk DS addr count del addrTable 5-1. Debugger Commands Continued MAW controller LUNdel device LUN del block # MAR controller LUN del device LUNTable 5-1. Debugger Commands Continued SYMS symbol-name SRS reg del exp del addr S D SET mmddyyhhmm n CAConﬁgure and Environment Commands This Appendix CoversConﬁguring the Board Information Block Page Setting Environment to Bug/Operating System ENV DTable A-1. ENV Command Parameters The parameters to be configured are listed in the following tableTable A-1. ENV Command Parameters Continued FFBFFFFCTable A-1. ENV Command Parameters Continued Table A-1. ENV Command Parameters Continued Table A-1. ENV Command Parameters Continued FFFFCE0FTable A-1. ENV Command Parameters Continued 01FFFFFFTable A-1. ENV Command Parameters Continued Guide01FF FFE1FFFFTable A-1. ENV Command Parameters Continued EFFFFFFFTable A-1. ENV Command Parameters Continued Table A-1. ENV Command Parameters Continued Configure and Environment Commands A-14BDisk/Tape Controller Data Disk/Tape Controller Modules SupportedDisk/Tape Controller Default Conﬁgurations $XXXXXXXXMVME327A -- 9 Devices MVME328 -- 14 DevicesIOT Command Parameters for Supported Floppy Types MVME350 -- 1 DeviceOther Characteristics IOT ParameterFloppy Types and Formats DSDD5Disk/Tape Controller Data Table C-1. Network Controller Access Data CNetwork Controller DataNetwork Controller Modules Supported Table C-1. Network Controller Access Data Continued DTroubleshooting the MVME187 Solving Startup Problems Table D-1. Troubleshooting StepsTable D-1. Troubleshooting Steps Continued Table D-1. Troubleshooting Steps Continued III. DebugTable D-1. Troubleshooting Steps Continued 3. When prompted to Update Non-Volatile RAM, type in187-Diag BREAKTable D-1. Troubleshooting Steps Continued Troubleshooting the MVME187 Solving Startup Problems EEIA-232-D Interconnections IntroductionTable E-1. EIA-232-D Interconnections GroundingLevels of Implementation Table E-1. EIA-232-D Interconnections ContinuedSignal Adaptations Sample ConﬁgurationsFigure E-1. Middle-of-the-Road EIA-232-D Conﬁguration Figure E-2. Minimum EIA-232-D Connection Proper Grounding EIA-232-D Interconnections Symbols IndexNumerics I N D E error codes support via 187Bug commands 4-15 via 187Bug system callsdefault configurations B-2 I N D EI N D E local bus local I/O devices 2-26 VMEbus 2-28 VMEbus short I/O I N D EI N D E I N D E see also CD2401 scientific notation 5-14 SCON LEDin NVRAM edge significant 1-2 level significantI N D E see also CD2401 serial port 1 5-8 serial port 2I N D E