Port Numbers, Offset Registers | Motorola MVME187 specification

Entering Debugger Command Lines

Offset Registers

Eight pseudo-registers (Z0 through Z7) called offset registers are used to simplify the debugging of relocatable and position- independent modules. The listing files in these types of programs usually start at an address (normally 0) that is not the one at which they are loaded, so it is harder to correlate addresses in the listing with addresses in the loaded program. The offset registers solve this problem by taking into account this difference and forcing the display of addresses in a relative address+offset format. Offset registers have adjustable ranges and may even have overlapping ranges. The range for each offset register is set by two addresses: base and top. Specifying the base and top addresses for an offset register sets its range. In the event that an address falls in two or more offset registers' ranges, the one that yields the least offset is chosen.

Note Relative addresses are limited to 1MB (5 digits), regardless of the range of the closest offset register.

Port Numbers

Some 187Bug commands give the user the option to choose the port to be used to input or output. Valid port numbers which may be used for these commands are:

1.MVME187 EIA-232-D Debug (Terminal Port 0 or 00) (PORT 1 on the MVME187 P2 connector). Sometimes known as the Òconsole portÓ, it is used for interactive user input/output by default.

2.MVME187 EIA-232-D (Terminal Port 1 or 01) (PORT 2 on the MVME187 P2 connector). Sometimes known as the Òhost portÓ, this is the default for downloading, uploading, concurrent mode, and transparent modes.

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Motorola MVME187 manual Port Numbers, Offset Registers

Contents

MVME187 Risc Single Board Computer Installation Guide Restricted Rights Legend Preface Assembly Item Board Description Safety Summary Safety Depends On You Copyright Motorola All Rights Reserved March Page Contents Page Page Page Page Page List of Figures List of Tables About this Manual This Chapter Covers Data and Address Parameter Numeric Formats Signal Name Conventions Assertion and Negation Conventions Data and Address Size DeﬁnitionsBig-Endian Byte Ordering Control and Status Bit Deﬁnitions True/False Bit State DeﬁnitionsBit Value Descriptions Related Documentation Document Set for MVME187-0xxBoardMotorola Description Publication Number Other Applicable Motorola Publications Additional Manuals for this BoardSingle Board Computers Scsi Software UserÕs Manual Motorola Description Part Number Description Non-Motorola Peripheral Controllers Publications Bundle SBCCOMPS/L Document Title Source Applicable Non-Motorola Publications Introduction to the MVME187 Installation Guide General Description Board Level Hardware Description Scsi Mass Storage Interface Onboard Memory Mezzanine Module Serial Ports Serial Function Synchronous Signals Bit RatesParallel Printer Port Ethernet Transceiver Interface 187Bug Firmware Features Features Speciﬁcations Characteristics SpeciÞcationsConformance to Requirements MVME187 General Speciﬁcations Connectors Board Level OverviewAdapters ASICs Transition Modules Bus Transfers VMEchip2 AsicPCCchip2 Asic Transfer type Can be Functional Description MEMC040 Memory Controller AsicMcecc Memory Controller Asic Front Panel Switches Front Panel Switches and LEDsSwitch Description Front Panel LEDs Data Bus Structure M88000 MPULocal Bus Arbitration Static RAM Programmable Eprom Features See Optional Sram Backup Power Source Select Header J6 on Optional Sram Battery Backup Onboard Dram Dram Programming Considerations Stacking Mezzanines Battery Backed Up RAM and Clock VMEbus Interface InterfacesSerial Port Interface Serial Interface Programming Considerations Status Pins Control PinsParallel Port Interface Ethernet Interface Scsi Interface Buffer Overruns Watchdog Timer Programmable Tick TimersLocal Bus Timeout Local Resources Memory Maps Local Bus Memory MapNormal Address Range Devices Local Bus Memory Map Address Software Devices Accessed Port SizeRange Inhibit Local I/O Devices Memory Map Address Range Devices Accessed Port Size $FFFE000B Iack Level VMEbus Accesses to the Local Bus VMEbus Memory MapVMEbus Short I/O Memory Map Unpacking the Equipment Hardware Preparation and Installation Install your MVME187 in the chassis Overview of Startup ProcedureStartup Overview Stage What you will need to do Refer to Prepare the MVME187 Complete the installation Stage What you will need to do Refer toConnect peripherals Package for Motorola 88K Modifying Conﬁguration before Installation Preparing the HardwareOption Modiﬁcation MVME187 Switches, Headers, Connectors, Fuses, and LEDs Checking the 187Bug EPROMs Jumper SettingsEprom Location Eprom Orientation General Purpose Software Readable Header J1 Optional Jumper Settings Bit J1 Pins Description Factory Settings for J1 General Purpose Readable JumpersJ1 Bit Descriptions Header ConÞguration Jumpers Number Description System Controller Header J2 Settings for J2 System Controller Header Serial Port 4 Clock Conﬁguration Select Headers J7 and J8 Optional Sram Backup Power Source Select Header J6 Primary source VMEbus Number Description Preparing the MVME187 for Installation MVME187 Preparation ProcedureAction Chassis Preparation/Slot Selection Procedure Preparing the System ChassisStep Action Installing the Hardware Installing the MVME187 in the ChassisMVME187 Installation Procedure Transition Modules and Adapter Boards Overview Typical Internal Scsi and Serial Port Connections Equipment Connections 10. Peripheral ConnectionsEquipment Type Connect Through Connecting Peripherals Installing Transition Modules and Adapter Boards Action Refer to 12. Peripheral Connection Procedures Using MVME712A/AM and MVME712B Typical Transition Module Peripheral Port Connectors 13. Installation Completion Procedure Completing the InstallationStarting the System 14. System Startup Overview If 187Bug is Board Mode Powering Up the SystemSystem Mode Initializing the Real-Time Clock 15. RTC Initialization Procedure Step Action Board Mode System ModeProgramming the PCCchip2 and VMEchip2 Global Bus Timeout Backplane Power ConnectionsSystem Considerations Memory Address Ranges Multiple Module Cage Conﬁguration Gcsr Location Monitor RegisterEthernet LAN +12 Vdc Fuse Storage and the Real-Time Clock Scsi Bus Termination Hardware Preparation and Installation Overview of M88000 Firmware Introduction to MVME187Bug Command Facilities Description of 187BugTrap #496 Routines Keyboard Control Debugger or Diagnostic Directories 187Bug Implementation Comparison with M68000-Based Firmware Memory Requirements Booting and Restarting 187Bug Autoboot Autoboot SequenceStarting Up 187Bug ROMboot Sequence ROMboot Network Boot Network Boot SequenceRequirement Optionally, with the ENV command Restarting the System Abort Reset Break Abort Sequence MPU Clock Speed Calculation SYSFAIL* Assertion/Negation Disk Support Facilities Disk I/O SupportParameter Tables Supported Controllers Device Probe Function Blocks Versus Sectors Disk I/O via 187Bug Commands BH Bootstrap and Halt Controller Command PacketsDisk I/O via 187Bug System Calls Default 187Bug Controller and Device Parameters Using When you invoke one Change Disk I/O Error CodesThese commands Status is Command BO or BH Network I/O Support Intel 82596 LAN Coprocessor Ethernet DriverUDP/IP Protocol Modules Network Boot Control Module Bootp Protocol ModuleRARP/ARP Protocol Modules Tftp Protocol Module Network I/O Error Codes Multiprocessor SupportMultiprocessor Control Register Mpcr Method Mpcr Powerup Sequence Mpcr Status CodesMultiprocessor Address Register Mpar Multiprocessor Support Global Control and Status Register Gcsr Method Diagnostic Facilities Diagnostic Monitor Commands/PreﬁxesCommand Description PreÞx Command Description Write loop enable Read loop enable Diagnostic Utilities Diagnostic Test Groups 187Bug Diagnostic Test Groups Debugger General Information Terminal Input/Output Control Entering Debugger Command Lines More characters to it. You can edit the line by Debugger Command Syntax Syntactic Variables Expression as a ParameterBase IdentiÞer Examples Address as a Parameter String Numeric Value LiteralExpression Result In Hex Address Formats Offset Registers Port Numbers Entering and Debugging Programs Creating a Program with the Assembler/DisassemblerDownloading an S-Record Object File Read the Program from Disk Calling System Utilities from User Programs 187Bug Vector Table and Workspace Preserving the Debugger Operating Environment Hardware Functions Floating Point SupportException Vectors Used by 187Bug CPU/MPU Registers Floating Point Data Types Integer Data Types Double Precision Real Single Precision Real Scientiﬁc Notation Debugger Commands 187Bug Debugger Command Set CS range B H W Cnfg I MENV D IOI C L Zn a Niot HANopa port Nopf port SYM addr RL addr B H WTime C L O VER E This Appendix Covers Conﬁguring the Board Information BlockCnfg IM Configure and Environment Commands Setting Environment to Bug/Operating System ENV Parameter and Options Default Meaning of Default Table A-1. ENV Command Parameters First location tested when the Bug LUN Network Auto Boot ConÞguration Memory Search Ending Address Slave address decoders setup Guide Base address of the VMEbus resource This will be the local bus address Table A-1. ENV Command Parameters Configure and Environment Commands Disk/Tape Controller Modules Supported Controller Type First SecondAddress $XXXXXXXX Disk/Tape Controller Default Conﬁgurations Controller LUN Address Device LUN Device Type MVME327A -- 9 Devices IOT Parameter Floppy Types and Formats IOT Command Parameters for Supported Floppy Types Other Characteristics Disk/Tape Controller Data Debugger Commands Debugger System Calls Table C-1. Network Controller Access DataNetwork Controller Modules Supported Address Interface $FFFFA400 Condition Possible Try This Problem Table D-1. Troubleshooting Steps Troubleshooting the MVME187 Solving Startup Problems Table D-1. Troubleshooting Steps Set mmddyyhhmm Return Envd ReturnReturn Env Return St ReturnDe Return Troubleshooting the MVME187 Solving Startup Problems Introduction EEIA-232-D Interconnections Table E-1. EIA-232-D Interconnections Signal Name and DescriptionPin Number Mnemonic Levels of Implementation Signal Name and Description Number Mnemonic Sample Conﬁgurations Signal Adaptations Figure E-1. Middle-of-the-Road EIA-232-D Conﬁguration Figure E-2. Minimum EIA-232-D Connection Proper Grounding EIA-232-D Interconnections Index Bootp Default configurations B-2 IN-12 Local bus Local I/O devices 2-26VMEbus 2-28VMEbus short I/O IN-14 See also CD2401 scientific notation 5-14 Scon LED Nvram XON/XOFF