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Motorola MVME187 manual Index, Symbols, Numerics

Models: MVME187

1 173

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Index

Index

Symbols

#496 system calls 4-16+12V LED 2-11

Numerics

100 ns SRAMs 2-13 187Bug

debugger command set 5-15firmware in EPROMs 2-4implementation 4-4

see also debug monitor and MVME187Bug

stack 4-5

vector table and workspace 5-10 27C102JK type EPROM 2-13

44-pin PLCC/CLCC EPROM 2-13

5-1/4 DS/DD 96 TPI floppy drive B-2 53C710 (SCSI Controller) 2-2282596CA 2-12,2-21

see also Ethernet and LAN 96-position DIN connectors 2-7

A

abort 4-10

ABORT switch 2-11

adapter board and transition module in- stallation 3-20

adapters 2-7

additional manuals for the MVME187 board 1-6

address 5-4

as a parameter 5-5 formats 5-6

address resolution protocol (ARP) 4-20 applicable Non-Motorola Publications

1-9

arguments 5-3 arithmetic operators 5-4 ASCII string 5-4assembler/disassembler 4-2,5-8 assertion and negation conventions 1-3 autoboot 4-6

B

backplane power connections 3-27 Backus-Naur 5-3

base and top addresses 5-7 base identifier 5-4

Battery Backed Up RAM (BBRAM) and clock 2-17

see also MK48T08 and NVRAM BH (Bootstrap and Halt) 4-16big-endian byte ordering 1-3 binary number 1-2

bit value descriptions 1-4 block diagram 2-7 blocks versus sectors 4-14

BO (Bootstrap Operating System) 4-15 board

information block A-1

level hardware description 2-1 level overview 2-7

select value 4-24 boldface string 5-3 Boot PROM 4-19 booting 187Bug 4-5

IN-9

Image 165

Motorola MVME187 manual Index, Symbols, Numerics

Contents

MVME187IG/D4 MVME187 RISC Single Board Computer Installation GuideRestricted Rights Legend Preface Do Not Service or Adjust Alone Safety Summary Safety Depends On YouUse Caution When Exposing or Handling the CRT Dangerous Procedure WarningsThis equipment generates, uses, and can radiate electro Page Contents Local Bus Arbitration M88000 MPU EPROM Programmable EPROM Features Front Panel Switches and LEDs Data Bus StructureStatic RAM Optional SRAM Battery Backup Onboard DRAM Battery Backed Up RAM and Clock VMEbus Interface I/O InterfacesInstalling the Hardware Installing the MVME187 in the Chassis Jumper Settings Optional Jumper SettingsCompleting the Installation 3-24 Starting the System Powering Up the System 3-25 Initializing the Real-Time ClockAutoboot Sequence 4-6 ROMboot ROMboot Sequence 4-7 Network Boot Booting and Restarting 187Bug 4-5 Starting Up 187Bug 4-6 AutobootNetwork Boot Sequence 4-8 Restarting the System Reset Abort Break BO Bootstrap Operating System 4-15 BH Bootstrap and Halt187Bug Diagnostic Test Groups 4-27 This Chapter Covers Multiprocessor Address Register MPAR 4-22 MPCR Powerup SequenceThe 187Bug Debugger Command Set 5-15 This Appendix Covers A-1 MPCR Status CodesSignal Adaptations E-4 Sample ConÞgurations E-4 Proper Grounding E-7 MVME187 General Block Diagram List of FiguresUsing MVME712A/AM and MVME712B Typical Transition Module Peripheral Port ConnectorsList of Tables 1Introduction to the MVME187 Installation Guide This Chapter CoversAbout this Manual Signal Name Conventions Terminology, Conventions, and Deﬁnitions Used in this ManualData and Address Parameter Numeric Formats Assertion and Negation Conventions Data and Address Size DeﬁnitionsBig-Endian Byte Ordering True/False Bit State Deﬁnitions Control and Status Bit DeﬁnitionsBit Value Descriptions The bit can be set and cleared under softwareDocument Set for MVME187-0xx Board Related DocumentationAdditional Manuals for this Board Other Applicable Motorola PublicationsAlso available but not included in the set Non-Motorola Peripheral Controllers Publications Bundle Data Sheet Introduction to the MVME187 Installation GuideMC68230 Parallel Interface Timer PI/T Data Sheet Part NumberANSI/IEEE Std Applicable Non-Motorola PublicationsData, IEC 821 BUS Sheet, order number1-10 Introduction to the MVME187 Installation GuideBoard Level Hardware Description General DescriptionThis Chapter Covers SCSI Mass Storage Interface Onboard Memory Mezzanine ModuleSerial Ports Parallel Printer PortEthernet Transceiver Interface 187Bug Firmware FeaturesFour 32-bit tick timers for periodic interrupts Watchdog timer Speciﬁcations Conformance to RequirementsTable 2-1. MVME187 General Speciﬁcations Figure 2-1. MVME187 General Block Diagram ConnectorsBoard Level Overview AdaptersASICs Transition ModulesVMEchip2 ASIC Table 2-2. Bus TransfersPCCchip2 ASIC Functional Description MEMC040 Memory Controller ASICMCECC Memory Controller ASIC Front Panel Switches and LEDs Table 2-3. Front Panel SwitchesTable 2-4. Front Panel LEDs Data Bus Structure M88000 MPULocal Bus Arbitration Programmable EPROM Features EPROMStatic RAM Optional SRAM Battery Backup Onboard DRAM DRAM Programming Considerations Stacking MezzaninesBattery Backed Up RAM and Clock VMEbus Interface I/O InterfacesSerial Port Interface Serial Interface Programming Considerations Parallel Port Interface Ethernet Interface Buffer Overruns SCSI InterfaceSCSI Termination Watchdog Timer Programmable Tick TimersLocal Bus Timeout Local ResourcesMemory Maps Local Bus Memory MapNormal Address Range Devices Table 2-5. Local Bus Memory Map Table 2-6. Local I/O Devices Memory Map Table 2-6. Local I/O Devices Memory Map Continued VMEbus Accesses to the Local Bus VMEbus Memory MapVMEbus Short I/O Memory Map Hardware Preparation and Installation Unpacking the EquipmentThis Chapter Covers Table 3-1. Startup Overview Overview of Startup Procedureobtain the Single Board Table 3-1. Startup Overview ContinuedComputer SCSI Software UserÕs ManualTable 3-1. Startup Overview Continued pageobtain the Debugging Modifying Conﬁguration before Installation Preparing the HardwareOption Modiﬁcation MVME Figure 3-1. MVME187 Switches, Headers, Connectors, Fuses, and LEDsChecking the 187Bug EPROMs Jumper SettingsEPROM Location EPROM OrientationOptional Jumper Settings General Purpose Software Readable Header J1Reserved/DeÞned Bits Table 3-2. J1 Bit Descriptions Table 3-3. Factory Settings for J1 General Purpose Readable JumpersGPI0 - GPI3 GPI4 - GPI7Table 3-4. Settings for J2 System Controller Header System Controller Header J2System Serial Port 4 Clock Conﬁguration Select Headers J7 and J8 Optional SRAM Backup Power Source Select Header J6Select Header Table 3-5. Settings for Optional J6 SRAM Backup Power SourceSelect Headers Table 3-6. Settings for J7 and J8 Serial Port 4 Clock ConﬁgurationSerial Port clockTable 3-7. MVME187 Preparation Procedure Preparing the MVME187 for InstallationPreparing the System Chassis Table 3-8. Chassis Preparation/Slot Selection ProcedureInstalling the Hardware Installing the MVME187 in the ChassisTable 3-9. MVME187 Installation Procedure Transition Modules and Adapter Boards Overview Installing the Hardware3-17 Figure 3-2. Typical Internal SCSI and Serial Port Connections Hardware Preparation and Installation3-18 Table 3-10. Peripheral Connections Equipment ConnectionsSome connection diagrams are in the Single Board Computer External SCSI drivesInstalling Transition Modules and Adapter Boards Connecting PeripheralsTable 3-11. Transition Module and Adapter Board Installation Overview parity disabled no parity Table 3-12. Peripheral Connection Proceduresbaud rate 9600 baud default baud rate of MVME187 ports at powerupFigure 3-3. Using MVME712A/AM and MVME712B MVME Figure 3-4. Typical Transition Module Peripheral Port Connectors712A To J10 onTable 3-13. Installation Completion Procedure Completing the InstallationStarting the System Table 3-14. System Startup OverviewInitializing the Real-Time Clock Powering Up the SystemExamining and/or Changing Environmental Parameters Board ModeProgramming the PCCchip2 and VMEchip2 Table 3-15. RTC Initialization ProcedureSET MMddyyhhmm+/-CALC 187-BugSET 0522961037 ReturnGlobal Bus Timeout Backplane Power ConnectionsSystem Considerations Memory Address RangesMultiple Module Cage Conﬁguration GCSR Location Monitor RegisterEthernet LAN +12 Vdc Fuse SCSI Bus Termination Storage and the Real-Time Clock187-Bugps Return 3-30 Hardware Preparation and InstallationIntroduction to MVME187Bug Debugger General InformationOverview of M88000 Firmware This Chapter CoversCommand Facilities Description of 187BugTrap #496 Routines Keyboard Control Debugger or Diagnostic Directories187Bug Implementation Comparison with M68000-Based FirmwareMemory Requirements Booting and Restarting 187BugAutoboot Autoboot SequenceStarting Up 187Bug ROMboot Sequence ROMbootNetwork Boot Sequence Network BootRestarting the System During COLD reset ResetDuring WARM reset AbortBreak Abort SequenceBreak Sequence SYSFAIL* Assertion/NegationMPU Clock Speed Calculation Disk Support Facilities Disk I/O SupportParameter Tables Supported ControllersDevice Probe Function Blocks Versus SectorsBO Bootstrap Operating System Disk I/O via 187Bug CommandsIOI Input/Output Inquiry IOP Physical I/O to DiskBH Bootstrap and Halt Controller Command PacketsDisk I/O via 187Bug System Calls Default 187Bug Controller and Device Parameters source Disk I/O Error CodesNetwork I/O Support Intel 82596 LAN Coprocessor Ethernet DriverUDP/IP Protocol Modules Network Boot Control Module BOOTP Protocol ModuleRARP/ARP Protocol Modules TFTP Protocol ModuleNetwork I/O Error Codes Multiprocessor SupportMultiprocessor Control Register MPCR Method MPCR Powerup Sequence MPCR Status CodesMultiprocessor Address Register MPAR 3. As the initialization proceeds, the execution path comes to the prompt routine Global Control and Status Register GCSR Method Table 4-1. Diagnostic Monitor Commands/Preﬁxes Diagnostic FacilitiesTable 4-1. Diagnostic Monitor Commands/Preﬁxes Table 4-2. Diagnostic UtilitiesCommand CommandTable 4-3. Diagnostic Test Groups 187Bug Diagnostic Test Groups4-28 Debugger General InformationEntering Debugger Command Lines Using the 187Bug DebuggerTerminal Input/Output Control This Chapter CoversUsing the 187Bug Debugger Debugger Command Syntax Expression as a Parameter Syntactic VariablesAddress as a Parameter Address Formats Offset Registers Port NumbersEntering and Debugging Programs Creating a Program with the Assembler/DisassemblerDownloading an S-Record Object File Read the Program from Disk Calling System Utilities from User Programs187Bug Vector Table and Workspace Preserving the Debugger Operating EnvironmentHardware Functions Floating Point SupportException Vectors Used by 187Bug CPU/MPU Registers1. The sign field is the first field and is a binary field Double Precision Real Single Precision Real2 hex digits. Bias = $7F 3 hex digits. Bias = $3FFScientiﬁc Notation Table 5-1. Debugger Commands The 187Bug Debugger Command SetAS addr BC range del addr B H WHE command Table 5-1. Debugger Commands ContinuedDMA range del addr del vdir del am del blk DS addr count del addrMAW controller LUN Table 5-1. Debugger Commands Continueddel device LUN del block # MAR controller LUN del device LUNSYMS symbol-name S Table 5-1. Debugger Commands ContinuedRS reg del exp del addr S D SET mmddyyhhmm n CAConﬁgure and Environment Commands This Appendix CoversConﬁguring the Board Information Block Page ENV D Setting Environment to Bug/Operating SystemThe parameters to be configured are listed in the following table Table A-1. ENV Command ParametersFFBFFFFC Table A-1. ENV Command Parameters ContinuedTable A-1. ENV Command Parameters Continued Table A-1. ENV Command Parameters Continued FFFFCE0F Table A-1. ENV Command Parameters Continued01FFFFFF Table A-1. ENV Command Parameters ContinuedGuide Table A-1. ENV Command Parameters Continued01FF FFE1FFFFEFFFFFFF Table A-1. ENV Command Parameters ContinuedTable A-1. ENV Command Parameters Continued Table A-1. ENV Command Parameters Continued A-14 Configure and Environment CommandsDisk/Tape Controller Modules Supported BDisk/Tape Controller Data$XXXXXXXX Disk/Tape Controller Default ConﬁgurationsMVME328 -- 14 Devices MVME327A -- 9 DevicesMVME350 -- 1 Device IOT Command Parameters for Supported Floppy TypesIOT Parameter Other CharacteristicsFloppy Types and Formats DSDD5Disk/Tape Controller Data Table C-1. Network Controller Access Data CNetwork Controller DataNetwork Controller Modules Supported Table C-1. Network Controller Access Data Continued Table D-1. Troubleshooting Steps DTroubleshooting the MVME187 Solving Startup ProblemsTable D-1. Troubleshooting Steps Continued III. Debug Table D-1. Troubleshooting Steps Continued3. When prompted to Update Non-Volatile RAM, type in Table D-1. Troubleshooting Steps Continued187-Diag BREAKTable D-1. Troubleshooting Steps Continued Troubleshooting the MVME187 Solving Startup Problems Introduction EEIA-232-D InterconnectionsGrounding Table E-1. EIA-232-D InterconnectionsTable E-1. EIA-232-D Interconnections Continued Levels of ImplementationSample Conﬁgurations Signal AdaptationsFigure E-1. Middle-of-the-Road EIA-232-D Conﬁguration Figure E-2. Minimum EIA-232-D Connection Proper Grounding EIA-232-D Interconnections Symbols IndexNumerics I N D E support via 187Bug commands 4-15 via 187Bug system calls error codesdefault configurations B-2 I N D EI N D E I N D E local bus local I/O devices 2-26 VMEbus 2-28 VMEbus short I/OI N D E see also CD2401 scientific notation 5-14 SCON LED I N D Eedge significant 1-2 level significant in NVRAMI N D E see also CD2401 serial port 1 5-8 serial port 2I N D E