System Considerations, Memory Address Ranges | Motorola MVME187

System Considerations

System Considerations

Backplane Power Connections

The MVME187 needs to draw power from both P1 and P2 of the VMEbus backplane. P2 is also used for the upper 16 bits of data for 32-bit transfers, and for the upper 8 address lines for extended addressing mode. The MVME187 may not operate properly without its main board connected to P1 and P2 of the VMEbus backplane.

Memory Address Ranges

Whether the MVME187 operates as a VMEbus master or as a VMEbus slave, it is configured for 32 bits of address and for 32 bits of data (A32/D32). However, it handles A16 or A24 devices in certain address ranges. D8 and/or D16 devices in the system must be handled by the MC88100 software. Refer to the memory maps in the Single Board Computer Programmer's Reference Guide as listed in Related Documentation in Chapter 1.

DRAM Addressing

The MVME187 contains shared onboard DRAM whose base address is software-selectable. Both the onboard processor and offboard VMEbus devices see this local DRAM at base physical address $00000000, as programmed by the MVME187Bug firmware. This may be changed, by software, to any other base address. Refer to the Single Board Computer Programmer's Reference Guide for details.

Global Bus Timeout

If the MVME187 tries to access offboard resources in a non-existent location, and is not system controller, and if the system does not have a global bus timeout, the MVME187 waits forever for the VMEbus cycle to complete. This would cause the system to hang up.

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Motorola MVME187 manual System Considerations, Backplane Power Connections, Memory Address Ranges, Dram Addressing

Contents

MVME187 Risc Single Board Computer Installation Guide Restricted Rights Legend Preface Assembly Item Board Description Safety Summary Safety Depends On You Copyright Motorola All Rights Reserved March Page Contents Page Page Page Page Page List of Figures List of Tables About this Manual This Chapter Covers Data and Address Parameter Numeric Formats Signal Name Conventions Data and Address Size Deﬁnitions Assertion and Negation ConventionsBig-Endian Byte Ordering True/False Bit State Deﬁnitions Control and Status Bit DeﬁnitionsBit Value Descriptions Document Set for MVME187-0xxBoard Related DocumentationMotorola Description Publication Number Motorola Description Additional Manuals for this BoardOther Applicable Motorola Publications Single Board Computers Scsi Software UserÕs Manual Part Number Description Non-Motorola Peripheral Controllers Publications Bundle SBCCOMPS/L Document Title Source Applicable Non-Motorola Publications Introduction to the MVME187 Installation Guide General Description Board Level Hardware Description Scsi Mass Storage Interface Onboard Memory Mezzanine Module Ethernet Transceiver Interface Serial Function Synchronous Signals Bit RatesSerial Ports Parallel Printer Port 187Bug Firmware Features Features MVME187 General Speciﬁcations Characteristics SpeciÞcationsSpeciﬁcations Conformance to Requirements Board Level Overview ConnectorsAdapters ASICs Transition Modules Transfer type Can be VMEchip2 AsicBus Transfers PCCchip2 Asic MEMC040 Memory Controller Asic Functional DescriptionMcecc Memory Controller Asic Front Panel LEDs Front Panel Switches and LEDsFront Panel Switches Switch Description M88000 MPU Data Bus StructureLocal Bus Arbitration Static RAM Programmable Eprom Features See Optional Sram Backup Power Source Select Header J6 on Optional Sram Battery Backup Onboard Dram Dram Programming Considerations Stacking Mezzanines Battery Backed Up RAM and Clock Interfaces VMEbus InterfaceSerial Port Interface Serial Interface Programming Considerations Control Pins Status PinsParallel Port Interface Ethernet Interface Scsi Interface Buffer Overruns Local Resources Programmable Tick TimersWatchdog Timer Local Bus Timeout Local Bus Memory Map Memory MapsNormal Address Range Devices Inhibit Address Software Devices Accessed Port SizeLocal Bus Memory Map Range Local I/O Devices Memory Map Address Range Devices Accessed Port Size $FFFE000B Iack Level VMEbus Memory Map VMEbus Accesses to the Local BusVMEbus Short I/O Memory Map Unpacking the Equipment Hardware Preparation and Installation Stage What you will need to do Refer to Prepare the MVME187 Overview of Startup ProcedureInstall your MVME187 in the chassis Startup Overview Stage What you will need to do Refer to Complete the installationConnect peripherals Package for Motorola 88K Preparing the Hardware Modifying Conﬁguration before InstallationOption Modiﬁcation MVME187 Switches, Headers, Connectors, Fuses, and LEDs Eprom Orientation Jumper SettingsChecking the 187Bug EPROMs Eprom Location General Purpose Software Readable Header J1 Optional Jumper Settings Header ConÞguration Jumpers Number Description Factory Settings for J1 General Purpose Readable JumpersBit J1 Pins Description J1 Bit Descriptions System Controller Header J2 Settings for J2 System Controller Header Serial Port 4 Clock Conﬁguration Select Headers J7 and J8 Optional Sram Backup Power Source Select Header J6 Primary source VMEbus Number Description MVME187 Preparation Procedure Preparing the MVME187 for InstallationAction Preparing the System Chassis Chassis Preparation/Slot Selection ProcedureStep Action Installing the MVME187 in the Chassis Installing the HardwareMVME187 Installation Procedure Transition Modules and Adapter Boards Overview Typical Internal Scsi and Serial Port Connections 10. Peripheral Connections Equipment ConnectionsEquipment Type Connect Through Connecting Peripherals Installing Transition Modules and Adapter Boards Action Refer to 12. Peripheral Connection Procedures Using MVME712A/AM and MVME712B Typical Transition Module Peripheral Port Connectors 14. System Startup Overview Completing the Installation13. Installation Completion Procedure Starting the System Initializing the Real-Time Clock Powering Up the SystemIf 187Bug is Board Mode System Mode Step Action Board Mode System Mode 15. RTC Initialization ProcedureProgramming the PCCchip2 and VMEchip2 Memory Address Ranges Backplane Power ConnectionsGlobal Bus Timeout System Considerations Gcsr Location Monitor Register Multiple Module Cage ConﬁgurationEthernet LAN +12 Vdc Fuse Storage and the Real-Time Clock Scsi Bus Termination Hardware Preparation and Installation Overview of M88000 Firmware Introduction to MVME187Bug Description of 187Bug Command FacilitiesTrap #496 Routines Keyboard Control Debugger or Diagnostic Directories 187Bug Implementation Comparison with M68000-Based Firmware Memory Requirements Booting and Restarting 187Bug Autoboot Sequence AutobootStarting Up 187Bug ROMboot Sequence ROMboot Network Boot Sequence Network BootRequirement Optionally, with the ENV command Restarting the System Abort Reset Break Abort Sequence MPU Clock Speed Calculation SYSFAIL* Assertion/Negation Supported Controllers Disk I/O SupportDisk Support Facilities Parameter Tables Device Probe Function Blocks Versus Sectors Disk I/O via 187Bug Commands Controller Command Packets BH Bootstrap and HaltDisk I/O via 187Bug System Calls Default 187Bug Controller and Device Parameters BO or BH Disk I/O Error CodesUsing When you invoke one Change These commands Status is Command Intel 82596 LAN Coprocessor Ethernet Driver Network I/O SupportUDP/IP Protocol Modules Tftp Protocol Module Bootp Protocol ModuleNetwork Boot Control Module RARP/ARP Protocol Modules Multiprocessor Support Network I/O Error CodesMultiprocessor Control Register Mpcr Method Mpcr Status Codes Mpcr Powerup SequenceMultiprocessor Address Register Mpar Multiprocessor Support Global Control and Status Register Gcsr Method Diagnostic Monitor Commands/Preﬁxes Diagnostic FacilitiesCommand Description PreÞx Command Description Write loop enable Read loop enable Diagnostic Utilities Diagnostic Test Groups 187Bug Diagnostic Test Groups Debugger General Information Terminal Input/Output Control Entering Debugger Command Lines More characters to it. You can edit the line by Debugger Command Syntax Expression as a Parameter Syntactic VariablesBase IdentiÞer Examples String Numeric Value Literal Address as a ParameterExpression Result In Hex Address Formats Offset Registers Port Numbers Creating a Program with the Assembler/Disassembler Entering and Debugging ProgramsDownloading an S-Record Object File Read the Program from Disk Calling System Utilities from User Programs 187Bug Vector Table and Workspace Preserving the Debugger Operating Environment CPU/MPU Registers Floating Point SupportHardware Functions Exception Vectors Used by 187Bug Floating Point Data Types Integer Data Types Double Precision Real Single Precision Real Scientiﬁc Notation Debugger Commands 187Bug Debugger Command Set IOI C L Cnfg I MCS range B H W ENV D Nopf port Niot HAZn a Nopa port VER E RL addr B H WSYM addr Time C L O Conﬁguring the Board Information Block This Appendix CoversCnfg IM Configure and Environment Commands Setting Environment to Bug/Operating System ENV Parameter and Options Default Meaning of Default Table A-1. ENV Command Parameters First location tested when the Bug LUN Network Auto Boot ConÞguration Memory Search Ending Address Slave address decoders setup Guide Base address of the VMEbus resource This will be the local bus address Table A-1. ENV Command Parameters Configure and Environment Commands Controller Type First Second Disk/Tape Controller Modules SupportedAddress $XXXXXXXX Disk/Tape Controller Default Conﬁgurations Controller LUN Address Device LUN Device Type MVME327A -- 9 Devices IOT Parameter Floppy Types and Formats IOT Command Parameters for Supported Floppy Types Other Characteristics Disk/Tape Controller Data Address Interface Table C-1. Network Controller Access DataDebugger Commands Debugger System Calls Network Controller Modules Supported $FFFFA400 Condition Possible Try This Problem Table D-1. Troubleshooting Steps Troubleshooting the MVME187 Solving Startup Problems Table D-1. Troubleshooting Steps Envd Return Set mmddyyhhmm ReturnReturn St Return Env ReturnDe Return Troubleshooting the MVME187 Solving Startup Problems Introduction EEIA-232-D Interconnections Number Mnemonic Signal Name and DescriptionTable E-1. EIA-232-D Interconnections Pin Levels of Implementation Signal Name and Description Number Mnemonic Sample Conﬁgurations Signal Adaptations Figure E-1. Middle-of-the-Road EIA-232-D Conﬁguration Figure E-2. Minimum EIA-232-D Connection Proper Grounding EIA-232-D Interconnections Index Bootp Default configurations B-2 IN-12 Local bus Local I/O devices 2-26VMEbus 2-28VMEbus short I/O IN-14 See also CD2401 scientific notation 5-14 Scon LED Nvram XON/XOFF