Motorola MVME187 manual System Considerations, Backplane Power Connections, Memory Address Ranges

System Considerations

System Considerations

Backplane Power Connections

The MVME187 needs to draw power from both P1 and P2 of the VMEbus backplane. P2 is also used for the upper 16 bits of data for 32-bit transfers, and for the upper 8 address lines for extended addressing mode. The MVME187 may not operate properly without its main board connected to P1 and P2 of the VMEbus backplane.

Memory Address Ranges

Whether the MVME187 operates as a VMEbus master or as a VMEbus slave, it is configured for 32 bits of address and for 32 bits of data (A32/D32). However, it handles A16 or A24 devices in certain address ranges. D8 and/or D16 devices in the system must be handled by the MC88100 software. Refer to the memory maps in the Single Board Computer Programmer's Reference Guide as listed in Related Documentation in Chapter 1.

DRAM Addressing

The MVME187 contains shared onboard DRAM whose base address is software-selectable. Both the onboard processor and offboard VMEbus devices see this local DRAM at base physical address $00000000, as programmed by the MVME187Bug firmware. This may be changed, by software, to any other base address. Refer to the Single Board Computer Programmer's Reference Guide for details.

Global Bus Timeout

If the MVME187 tries to access offboard resources in a non-existent location, and is not system controller, and if the system does not have a global bus timeout, the MVME187 waits forever for the VMEbus cycle to complete. This would cause the system to hang up.

3

3-27