Manuals / Motorola / Computer Equipment / Computer Hardware

Motorola MVME187 manual Figure E-1. Middle-of-the-Road EIA-232-D Conﬁguration

Models: MVME187

1 173

Page 161

Figure E-1. Middle-of-the-Road EIA-232-D Conﬁguration

Levels of Implementation

SERIAL PORT
		1488
TXD					RXD	3
						3
			1489A
RXD					TXD	2
RXD						2
		39kΩ
		-12V			NC	1
RTS					NC	1	E
RTS		+12V				CONNECTOR	E
	LS08	+12V				TO
	LS08					TO
		470Ω	470Ω	470Ω		TERMINAL
CTS					CTS
					CTS	5
					DSR	5
	OPTIONAL				DSR	6
	HARDWARE					6
DCD	HARDWARE				DCD
DCD	TRANSPARENT				DCD	8
	TRANSPARENT					8
	MODE				SIG GND
					SIG GND	7
						7
TXC						CHASSIS GND
RXC		LOGIC				CHASSIS GND
RXC	LS08	GND
		+12V			SIG GND
					SIG GND

		470Ω	7
		470Ω	1
		NC	1
		DTR	20
		1488	20
SERIAL PORT		1488
SERIAL PORT		TXD
		TXD	2
TXD			2
TXD		1489A
		1489A
		RXD	3
RXD			3	CONNECTOR
	39kΩ			CONNECTOR
	39kΩ			TO
-12V				TO
-12V		1488		MODEM
		1488		MODEM
RTS		RTS	4	OR
RTS			4	HOST SYSTEM
	470Ω
+12V		1489A
		1489A
CTS		CTS	5
CTS			5
	39kΩ	470Ω
		470Ω
-12V		+12V
		1489A
		DCD
DCD			6
TXC		39kΩ
TXC		-12V
		-12V
RXC
				cb181 9210
Figure E-1. Middle-of-the-Road EIA-232-D Conﬁguration

E-5

Page 161

Image 161

Motorola MVME187 manual Figure E-1. Middle-of-the-Road EIA-232-D Conﬁguration

Contents

MVME187IG/D4 MVME187 RISC Single Board Computer Installation GuideRestricted Rights Legend Preface Do Not Service or Adjust Alone Safety Summary Safety Depends On YouUse Caution When Exposing or Handling the CRT Dangerous Procedure WarningsThis equipment generates, uses, and can radiate electro Page Contents Local Bus Arbitration M88000 MPU EPROM Programmable EPROM Features Front Panel Switches and LEDs Data Bus StructureStatic RAM Optional SRAM Battery Backup Onboard DRAM Battery Backed Up RAM and Clock VMEbus Interface I/O InterfacesInstalling the Hardware Installing the MVME187 in the Chassis Jumper Settings Optional Jumper SettingsCompleting the Installation 3-24 Starting the System Powering Up the System 3-25 Initializing the Real-Time ClockAutoboot Sequence 4-6 ROMboot ROMboot Sequence 4-7 Network Boot Booting and Restarting 187Bug 4-5 Starting Up 187Bug 4-6 AutobootNetwork Boot Sequence 4-8 Restarting the System Reset Abort Break BO Bootstrap Operating System 4-15 BH Bootstrap and Halt187Bug Diagnostic Test Groups 4-27 This Chapter Covers Multiprocessor Address Register MPAR 4-22 MPCR Powerup SequenceThe 187Bug Debugger Command Set 5-15 This Appendix Covers A-1 MPCR Status CodesSignal Adaptations E-4 Sample ConÞgurations E-4 Proper Grounding E-7 MVME187 General Block Diagram List of FiguresUsing MVME712A/AM and MVME712B Typical Transition Module Peripheral Port ConnectorsList of Tables About this Manual 1Introduction to the MVME187 Installation GuideThis Chapter Covers Data and Address Parameter Numeric Formats Signal Name ConventionsTerminology, Conventions, and Deﬁnitions Used in this Manual Big-Endian Byte Ordering Assertion and Negation ConventionsData and Address Size Deﬁnitions True/False Bit State Deﬁnitions Control and Status Bit DeﬁnitionsBit Value Descriptions The bit can be set and cleared under softwareDocument Set for MVME187-0xx Board Related DocumentationAlso available but not included in the set Additional Manuals for this BoardOther Applicable Motorola Publications Non-Motorola Peripheral Controllers Publications Bundle Data Sheet Introduction to the MVME187 Installation GuideMC68230 Parallel Interface Timer PI/T Data Sheet Part NumberANSI/IEEE Std Applicable Non-Motorola PublicationsData, IEC 821 BUS Sheet, order number1-10 Introduction to the MVME187 Installation GuideThis Chapter Covers Board Level Hardware DescriptionGeneral Description SCSI Mass Storage Interface Onboard Memory Mezzanine ModuleEthernet Transceiver Interface Serial PortsParallel Printer Port 187Bug Firmware FeaturesFour 32-bit tick timers for periodic interrupts Watchdog timer Table 2-1. MVME187 General Speciﬁcations SpeciﬁcationsConformance to Requirements Figure 2-1. MVME187 General Block Diagram ConnectorsBoard Level Overview AdaptersASICs Transition ModulesPCCchip2 ASIC VMEchip2 ASICTable 2-2. Bus Transfers MCECC Memory Controller ASIC Functional DescriptionMEMC040 Memory Controller ASIC Table 2-4. Front Panel LEDs Front Panel Switches and LEDsTable 2-3. Front Panel Switches Local Bus Arbitration Data Bus StructureM88000 MPU Static RAM Programmable EPROM FeaturesEPROM Optional SRAM Battery Backup Onboard DRAM DRAM Programming Considerations Stacking MezzaninesBattery Backed Up RAM and Clock Serial Port Interface VMEbus InterfaceI/O Interfaces Serial Interface Programming Considerations Parallel Port Interface Ethernet Interface SCSI Termination Buffer OverrunsSCSI Interface Watchdog Timer Programmable Tick TimersLocal Bus Timeout Local ResourcesNormal Address Range Devices Memory MapsLocal Bus Memory Map Table 2-5. Local Bus Memory Map Table 2-6. Local I/O Devices Memory Map Table 2-6. Local I/O Devices Memory Map Continued VMEbus Short I/O Memory Map VMEbus Accesses to the Local BusVMEbus Memory Map This Chapter Covers Hardware Preparation and InstallationUnpacking the Equipment Table 3-1. Startup Overview Overview of Startup Procedureobtain the Single Board Table 3-1. Startup Overview ContinuedComputer SCSI Software UserÕs Manualobtain the Debugging Table 3-1. Startup Overview Continuedpage Option Modiﬁcation Modifying Conﬁguration before InstallationPreparing the Hardware MVME Figure 3-1. MVME187 Switches, Headers, Connectors, Fuses, and LEDsChecking the 187Bug EPROMs Jumper SettingsEPROM Location EPROM OrientationReserved/DeÞned Bits Optional Jumper SettingsGeneral Purpose Software Readable Header J1 Table 3-2. J1 Bit Descriptions Table 3-3. Factory Settings for J1 General Purpose Readable JumpersGPI0 - GPI3 GPI4 - GPI7System Table 3-4. Settings for J2 System Controller HeaderSystem Controller Header J2 Serial Port 4 Clock Conﬁguration Select Headers J7 and J8 Optional SRAM Backup Power Source Select Header J6Select Header Table 3-5. Settings for Optional J6 SRAM Backup Power SourceSelect Headers Table 3-6. Settings for J7 and J8 Serial Port 4 Clock ConﬁgurationSerial Port clockTable 3-7. MVME187 Preparation Procedure Preparing the MVME187 for InstallationPreparing the System Chassis Table 3-8. Chassis Preparation/Slot Selection ProcedureTable 3-9. MVME187 Installation Procedure Installing the HardwareInstalling the MVME187 in the Chassis 3-17 Transition Modules and Adapter Boards OverviewInstalling the Hardware 3-18 Figure 3-2. Typical Internal SCSI and Serial Port ConnectionsHardware Preparation and Installation Table 3-10. Peripheral Connections Equipment ConnectionsSome connection diagrams are in the Single Board Computer External SCSI drivesTable 3-11. Transition Module and Adapter Board Installation Overview Installing Transition Modules and Adapter BoardsConnecting Peripherals parity disabled no parity Table 3-12. Peripheral Connection Proceduresbaud rate 9600 baud default baud rate of MVME187 ports at powerupFigure 3-3. Using MVME712A/AM and MVME712B MVME Figure 3-4. Typical Transition Module Peripheral Port Connectors712A To J10 onTable 3-13. Installation Completion Procedure Completing the InstallationStarting the System Table 3-14. System Startup OverviewInitializing the Real-Time Clock Powering Up the SystemExamining and/or Changing Environmental Parameters Board ModeProgramming the PCCchip2 and VMEchip2 Table 3-15. RTC Initialization ProcedureSET MMddyyhhmm+/-CALC 187-BugSET 0522961037 ReturnGlobal Bus Timeout Backplane Power ConnectionsSystem Considerations Memory Address RangesEthernet LAN +12 Vdc Fuse Multiple Module Cage ConﬁgurationGCSR Location Monitor Register 187-Bugps Return SCSI Bus TerminationStorage and the Real-Time Clock 3-30 Hardware Preparation and InstallationIntroduction to MVME187Bug Debugger General InformationOverview of M88000 Firmware This Chapter CoversTrap #496 Routines Command FacilitiesDescription of 187Bug Keyboard Control Debugger or Diagnostic Directories187Bug Implementation Comparison with M68000-Based FirmwareMemory Requirements Booting and Restarting 187BugStarting Up 187Bug AutobootAutoboot Sequence ROMboot Sequence ROMbootNetwork Boot Sequence Network BootRestarting the System During COLD reset ResetDuring WARM reset AbortBreak Abort SequenceMPU Clock Speed Calculation Break SequenceSYSFAIL* Assertion/Negation Disk Support Facilities Disk I/O SupportParameter Tables Supported ControllersDevice Probe Function Blocks Versus SectorsBO Bootstrap Operating System Disk I/O via 187Bug CommandsIOI Input/Output Inquiry IOP Physical I/O to DiskDisk I/O via 187Bug System Calls BH Bootstrap and HaltController Command Packets Default 187Bug Controller and Device Parameters source Disk I/O Error CodesUDP/IP Protocol Modules Network I/O SupportIntel 82596 LAN Coprocessor Ethernet Driver Network Boot Control Module BOOTP Protocol ModuleRARP/ARP Protocol Modules TFTP Protocol ModuleMultiprocessor Control Register MPCR Method Network I/O Error CodesMultiprocessor Support Multiprocessor Address Register MPAR MPCR Powerup SequenceMPCR Status Codes 3. As the initialization proceeds, the execution path comes to the prompt routine Global Control and Status Register GCSR Method Table 4-1. Diagnostic Monitor Commands/Preﬁxes Diagnostic FacilitiesTable 4-1. Diagnostic Monitor Commands/Preﬁxes Table 4-2. Diagnostic UtilitiesCommand CommandTable 4-3. Diagnostic Test Groups 187Bug Diagnostic Test Groups4-28 Debugger General InformationEntering Debugger Command Lines Using the 187Bug DebuggerTerminal Input/Output Control This Chapter CoversUsing the 187Bug Debugger Debugger Command Syntax Expression as a Parameter Syntactic VariablesAddress as a Parameter Address Formats Offset Registers Port NumbersDownloading an S-Record Object File Entering and Debugging ProgramsCreating a Program with the Assembler/Disassembler Read the Program from Disk Calling System Utilities from User Programs187Bug Vector Table and Workspace Preserving the Debugger Operating EnvironmentHardware Functions Floating Point SupportException Vectors Used by 187Bug CPU/MPU Registers1. The sign field is the first field and is a binary field Double Precision Real Single Precision Real2 hex digits. Bias = $7F 3 hex digits. Bias = $3FFScientiﬁc Notation Table 5-1. Debugger Commands The 187Bug Debugger Command SetAS addr BC range del addr B H WHE command Table 5-1. Debugger Commands ContinuedDMA range del addr del vdir del am del blk DS addr count del addrMAW controller LUN Table 5-1. Debugger Commands Continueddel device LUN del block # MAR controller LUN del device LUNSYMS symbol-name S Table 5-1. Debugger Commands ContinuedRS reg del exp del addr S D SET mmddyyhhmm n CConﬁguring the Board Information Block AConﬁgure and Environment CommandsThis Appendix Covers Page ENV D Setting Environment to Bug/Operating SystemThe parameters to be configured are listed in the following table Table A-1. ENV Command ParametersFFBFFFFC Table A-1. ENV Command Parameters ContinuedTable A-1. ENV Command Parameters Continued Table A-1. ENV Command Parameters Continued FFFFCE0F Table A-1. ENV Command Parameters Continued01FFFFFF Table A-1. ENV Command Parameters ContinuedGuide Table A-1. ENV Command Parameters Continued01FF FFE1FFFFEFFFFFFF Table A-1. ENV Command Parameters ContinuedTable A-1. ENV Command Parameters Continued Table A-1. ENV Command Parameters Continued A-14 Configure and Environment CommandsDisk/Tape Controller Modules Supported BDisk/Tape Controller Data$XXXXXXXX Disk/Tape Controller Default ConﬁgurationsMVME328 -- 14 Devices MVME327A -- 9 DevicesMVME350 -- 1 Device IOT Command Parameters for Supported Floppy TypesIOT Parameter Other CharacteristicsFloppy Types and Formats DSDD5Disk/Tape Controller Data Network Controller Modules Supported Table C-1. Network Controller Access DataCNetwork Controller Data Table C-1. Network Controller Access Data Continued Table D-1. Troubleshooting Steps DTroubleshooting the MVME187 Solving Startup ProblemsTable D-1. Troubleshooting Steps Continued III. Debug Table D-1. Troubleshooting Steps Continued3. When prompted to Update Non-Volatile RAM, type in Table D-1. Troubleshooting Steps Continued187-Diag BREAKTable D-1. Troubleshooting Steps Continued Troubleshooting the MVME187 Solving Startup Problems Introduction EEIA-232-D InterconnectionsGrounding Table E-1. EIA-232-D InterconnectionsTable E-1. EIA-232-D Interconnections Continued Levels of ImplementationSample Conﬁgurations Signal AdaptationsFigure E-1. Middle-of-the-Road EIA-232-D Conﬁguration Figure E-2. Minimum EIA-232-D Connection Proper Grounding EIA-232-D Interconnections Numerics SymbolsIndex I N D E support via 187Bug commands 4-15 via 187Bug system calls error codesdefault configurations B-2 I N D EI N D E I N D E local bus local I/O devices 2-26 VMEbus 2-28 VMEbus short I/OI N D E see also CD2401 scientific notation 5-14 SCON LED I N D Eedge significant 1-2 level significant in NVRAMI N D E see also CD2401 serial port 1 5-8 serial port 2I N D E