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Motorola MVME187 manual Onboard Memory Mezzanine Module, SCSI Mass Storage Interface

Models: MVME187

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Onboard Memory Mezzanine Module

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Board Level Hardware Description

Onboard Memory Mezzanine Module

The MVME187 onboard DRAM mezzanine boards are available in different sizes and with programmable parity protection or Error Checking and Correction (ECC) protection.

❏The main board and a single mezzanine board together take one slot.

❏Motorola software supports mixed parity and ECC memory boards on the same main board.

❏Mezzanine board sizes are 4, 8, 16, or 32 MB (parity), or 4, 8, 16, 32, 64, or 128 MB (ECC);

ÐTwo mezzanine boards may be stacked to provide 256MB of onboard RAM (ECC) or 64 MB (parity). The stacked configuration requires two VMEbus slots.

❏The DRAM is four-way interleaved to efficiently support cache burst cycles.

❏The parity mezzanines are only supported on 25 MHz main boards.

A functional description of the Onboard DRAM starts on page 2-15.

SCSI Mass Storage Interface

The MVME187 provides for mass storage subsystems through the industry-standard SCSI bus. These subsystems may include

❏Hard and floppy disk drives

❏Streaming tape drives

❏Other mass storage devices.

A functional description of the SCSI Interface starts on page 2-22.

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Motorola MVME187 manual Onboard Memory Mezzanine Module, SCSI Mass Storage Interface

Contents

MVME187 RISC Single Board Computer Installation Guide MVME187IG/D4Restricted Rights Legend Preface Use Caution When Exposing or Handling the CRT Safety Summary Safety Depends On YouDo Not Service or Adjust Alone Dangerous Procedure WarningsThis equipment generates, uses, and can radiate electro Page Contents Static RAM Optional SRAM Battery Backup Onboard DRAM Front Panel Switches and LEDs Data Bus StructureLocal Bus Arbitration M88000 MPU EPROM Programmable EPROM Features Battery Backed Up RAM and Clock VMEbus Interface I/O InterfacesCompleting the Installation 3-24 Starting the System Jumper Settings Optional Jumper SettingsInstalling the Hardware Installing the MVME187 in the Chassis Powering Up the System 3-25 Initializing the Real-Time ClockNetwork Boot Sequence 4-8 Restarting the System Reset Abort Break Booting and Restarting 187Bug 4-5 Starting Up 187Bug 4-6 AutobootAutoboot Sequence 4-6 ROMboot ROMboot Sequence 4-7 Network Boot BO Bootstrap Operating System 4-15 BH Bootstrap and HaltThe 187Bug Debugger Command Set 5-15 This Appendix Covers A-1 Multiprocessor Address Register MPAR 4-22 MPCR Powerup Sequence187Bug Diagnostic Test Groups 4-27 This Chapter Covers MPCR Status CodesSignal Adaptations E-4 Sample ConÞgurations E-4 Proper Grounding E-7 Using MVME712A/AM and MVME712B List of FiguresMVME187 General Block Diagram Typical Transition Module Peripheral Port ConnectorsList of Tables About this Manual 1Introduction to the MVME187 Installation GuideThis Chapter Covers Data and Address Parameter Numeric Formats Signal Name ConventionsTerminology, Conventions, and Deﬁnitions Used in this Manual Big-Endian Byte Ordering Assertion and Negation ConventionsData and Address Size Deﬁnitions Bit Value Descriptions Control and Status Bit DeﬁnitionsTrue/False Bit State Deﬁnitions The bit can be set and cleared under softwareRelated Documentation Document Set for MVME187-0xx BoardAlso available but not included in the set Additional Manuals for this BoardOther Applicable Motorola Publications Non-Motorola Peripheral Controllers Publications Bundle MC68230 Parallel Interface Timer PI/T Data Sheet Introduction to the MVME187 Installation GuideData Sheet Part NumberData, IEC 821 BUS Applicable Non-Motorola PublicationsANSI/IEEE Std Sheet, order numberIntroduction to the MVME187 Installation Guide 1-10This Chapter Covers Board Level Hardware DescriptionGeneral Description Onboard Memory Mezzanine Module SCSI Mass Storage InterfaceEthernet Transceiver Interface Serial PortsParallel Printer Port Features 187Bug FirmwareFour 32-bit tick timers for periodic interrupts Watchdog timer Table 2-1. MVME187 General Speciﬁcations SpeciﬁcationsConformance to Requirements Board Level Overview ConnectorsFigure 2-1. MVME187 General Block Diagram AdaptersTransition Modules ASICsPCCchip2 ASIC VMEchip2 ASICTable 2-2. Bus Transfers MCECC Memory Controller ASIC Functional DescriptionMEMC040 Memory Controller ASIC Table 2-4. Front Panel LEDs Front Panel Switches and LEDsTable 2-3. Front Panel Switches Local Bus Arbitration Data Bus StructureM88000 MPU Static RAM Programmable EPROM FeaturesEPROM Optional SRAM Battery Backup Onboard DRAM Stacking Mezzanines DRAM Programming ConsiderationsBattery Backed Up RAM and Clock Serial Port Interface VMEbus InterfaceI/O Interfaces Serial Interface Programming Considerations Parallel Port Interface Ethernet Interface SCSI Termination Buffer OverrunsSCSI Interface Local Bus Timeout Programmable Tick TimersWatchdog Timer Local ResourcesNormal Address Range Devices Memory MapsLocal Bus Memory Map Table 2-5. Local Bus Memory Map Table 2-6. Local I/O Devices Memory Map Table 2-6. Local I/O Devices Memory Map Continued VMEbus Short I/O Memory Map VMEbus Accesses to the Local BusVMEbus Memory Map This Chapter Covers Hardware Preparation and InstallationUnpacking the Equipment Overview of Startup Procedure Table 3-1. Startup OverviewComputer SCSI Software Table 3-1. Startup Overview Continuedobtain the Single Board UserÕs Manualobtain the Debugging Table 3-1. Startup Overview Continuedpage Option Modiﬁcation Modifying Conﬁguration before InstallationPreparing the Hardware Figure 3-1. MVME187 Switches, Headers, Connectors, Fuses, and LEDs MVMEEPROM Location Jumper SettingsChecking the 187Bug EPROMs EPROM OrientationReserved/DeÞned Bits Optional Jumper SettingsGeneral Purpose Software Readable Header J1 GPI0 - GPI3 Table 3-3. Factory Settings for J1 General Purpose Readable JumpersTable 3-2. J1 Bit Descriptions GPI4 - GPI7System Table 3-4. Settings for J2 System Controller HeaderSystem Controller Header J2 Optional SRAM Backup Power Source Select Header J6 Serial Port 4 Clock Conﬁguration Select Headers J7 and J8Table 3-5. Settings for Optional J6 SRAM Backup Power Source Select HeaderSerial Port Table 3-6. Settings for J7 and J8 Serial Port 4 Clock ConﬁgurationSelect Headers clockPreparing the MVME187 for Installation Table 3-7. MVME187 Preparation ProcedureTable 3-8. Chassis Preparation/Slot Selection Procedure Preparing the System ChassisTable 3-9. MVME187 Installation Procedure Installing the HardwareInstalling the MVME187 in the Chassis 3-17 Transition Modules and Adapter Boards OverviewInstalling the Hardware 3-18 Figure 3-2. Typical Internal SCSI and Serial Port ConnectionsHardware Preparation and Installation Some connection diagrams are in the Single Board Computer Equipment ConnectionsTable 3-10. Peripheral Connections External SCSI drivesTable 3-11. Transition Module and Adapter Board Installation Overview Installing Transition Modules and Adapter BoardsConnecting Peripherals baud rate 9600 baud default baud rate of MVME187 ports at Table 3-12. Peripheral Connection Proceduresparity disabled no parity powerupFigure 3-3. Using MVME712A/AM and MVME712B 712A Figure 3-4. Typical Transition Module Peripheral Port ConnectorsMVME To J10 onStarting the System Completing the InstallationTable 3-13. Installation Completion Procedure Table 3-14. System Startup OverviewExamining and/or Changing Environmental Parameters Powering Up the SystemInitializing the Real-Time Clock Board ModeSET MMddyyhhmm+/-CALC Table 3-15. RTC Initialization ProcedureProgramming the PCCchip2 and VMEchip2 187-BugSET 0522961037 ReturnSystem Considerations Backplane Power ConnectionsGlobal Bus Timeout Memory Address RangesEthernet LAN +12 Vdc Fuse Multiple Module Cage ConﬁgurationGCSR Location Monitor Register 187-Bugps Return SCSI Bus TerminationStorage and the Real-Time Clock Hardware Preparation and Installation 3-30Overview of M88000 Firmware Debugger General InformationIntroduction to MVME187Bug This Chapter CoversTrap #496 Routines Command FacilitiesDescription of 187Bug Debugger or Diagnostic Directories Keyboard ControlComparison with M68000-Based Firmware 187Bug ImplementationBooting and Restarting 187Bug Memory RequirementsStarting Up 187Bug AutobootAutoboot Sequence ROMboot ROMboot SequenceNetwork Boot Network Boot SequenceRestarting the System During WARM reset ResetDuring COLD reset AbortAbort Sequence BreakMPU Clock Speed Calculation Break SequenceSYSFAIL* Assertion/Negation Parameter Tables Disk I/O SupportDisk Support Facilities Supported ControllersBlocks Versus Sectors Device Probe FunctionIOI Input/Output Inquiry Disk I/O via 187Bug CommandsBO Bootstrap Operating System IOP Physical I/O to DiskDisk I/O via 187Bug System Calls BH Bootstrap and HaltController Command Packets Default 187Bug Controller and Device Parameters Disk I/O Error Codes sourceUDP/IP Protocol Modules Network I/O SupportIntel 82596 LAN Coprocessor Ethernet Driver RARP/ARP Protocol Modules BOOTP Protocol ModuleNetwork Boot Control Module TFTP Protocol ModuleMultiprocessor Control Register MPCR Method Network I/O Error CodesMultiprocessor Support Multiprocessor Address Register MPAR MPCR Powerup SequenceMPCR Status Codes 3. As the initialization proceeds, the execution path comes to the prompt routine Global Control and Status Register GCSR Method Diagnostic Facilities Table 4-1. Diagnostic Monitor Commands/PreﬁxesCommand Table 4-2. Diagnostic UtilitiesTable 4-1. Diagnostic Monitor Commands/Preﬁxes Command187Bug Diagnostic Test Groups Table 4-3. Diagnostic Test GroupsDebugger General Information 4-28Terminal Input/Output Control Using the 187Bug DebuggerEntering Debugger Command Lines This Chapter CoversUsing the 187Bug Debugger Debugger Command Syntax Syntactic Variables Expression as a ParameterAddress as a Parameter Address Formats Port Numbers Offset RegistersDownloading an S-Record Object File Entering and Debugging ProgramsCreating a Program with the Assembler/Disassembler Calling System Utilities from User Programs Read the Program from DiskPreserving the Debugger Operating Environment 187Bug Vector Table and WorkspaceException Vectors Used by 187Bug Floating Point SupportHardware Functions CPU/MPU Registers1. The sign field is the first field and is a binary field 2 hex digits. Bias = $7F Single Precision RealDouble Precision Real 3 hex digits. Bias = $3FFScientiﬁc Notation AS addr The 187Bug Debugger Command SetTable 5-1. Debugger Commands BC range del addr B H WDMA range del addr del vdir del am del blk Table 5-1. Debugger Commands ContinuedHE command DS addr count del addrdel device LUN del block # Table 5-1. Debugger Commands ContinuedMAW controller LUN MAR controller LUN del device LUNRS reg del exp del addr S D Table 5-1. Debugger Commands ContinuedSYMS symbol-name S SET mmddyyhhmm n CConﬁguring the Board Information Block AConﬁgure and Environment CommandsThis Appendix Covers Page Setting Environment to Bug/Operating System ENV DTable A-1. ENV Command Parameters The parameters to be configured are listed in the following tableTable A-1. ENV Command Parameters Continued FFBFFFFCTable A-1. ENV Command Parameters Continued Table A-1. ENV Command Parameters Continued Table A-1. ENV Command Parameters Continued FFFFCE0FTable A-1. ENV Command Parameters Continued 01FFFFFF01FF Table A-1. ENV Command Parameters ContinuedGuide FFE1FFFFTable A-1. ENV Command Parameters Continued EFFFFFFFTable A-1. ENV Command Parameters Continued Table A-1. ENV Command Parameters Continued Configure and Environment Commands A-14BDisk/Tape Controller Data Disk/Tape Controller Modules SupportedDisk/Tape Controller Default Conﬁgurations $XXXXXXXXMVME327A -- 9 Devices MVME328 -- 14 DevicesIOT Command Parameters for Supported Floppy Types MVME350 -- 1 DeviceFloppy Types and Formats Other CharacteristicsIOT Parameter DSDD5Disk/Tape Controller Data Network Controller Modules Supported Table C-1. Network Controller Access DataCNetwork Controller Data Table C-1. Network Controller Access Data Continued DTroubleshooting the MVME187 Solving Startup Problems Table D-1. Troubleshooting StepsTable D-1. Troubleshooting Steps Continued Table D-1. Troubleshooting Steps Continued III. Debug187-Diag Table D-1. Troubleshooting Steps Continued3. When prompted to Update Non-Volatile RAM, type in BREAKTable D-1. Troubleshooting Steps Continued Troubleshooting the MVME187 Solving Startup Problems EEIA-232-D Interconnections IntroductionTable E-1. EIA-232-D Interconnections GroundingLevels of Implementation Table E-1. EIA-232-D Interconnections ContinuedSignal Adaptations Sample ConﬁgurationsFigure E-1. Middle-of-the-Road EIA-232-D Conﬁguration Figure E-2. Minimum EIA-232-D Connection Proper Grounding EIA-232-D Interconnections Numerics SymbolsIndex I N D E default configurations B-2 error codessupport via 187Bug commands 4-15 via 187Bug system calls I N D EI N D E local bus local I/O devices 2-26 VMEbus 2-28 VMEbus short I/O I N D EI N D E I N D E see also CD2401 scientific notation 5-14 SCON LEDI N D E in NVRAMedge significant 1-2 level significant see also CD2401 serial port 1 5-8 serial port 2I N D E