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Motorola Debugger General Information, Introduction to MVME187Bug, Overview of M88000 Firmware

Models: MVME187

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Debugger General Information

This Chapter Covers

❏An introduction to the MVME187Bug firmware package

❏Booting and restarting 187Bug

❏Disk input/output support capabilities

❏Network support capabilities

Introduction to MVME187Bug

This section covers:

❏Overview of M88000 firmware

❏Description of 187Bug

❏Comparison with M68000-based firmware

❏187Bug implementation

❏Memory requirements

Overview of M88000 Firmware

The firmware for the M88000-based (88K) series of board and system level products has a common genealogy, deriving from the BUG firmware currently used on all Motorola M68000-based CPU modules. The M88000 firmware family provides a high degree of functionality and user friendliness, and yet stresses portability and ease of maintenance. This member of the M88000 firmware family is implemented on the MVME187 RISC Single Board Computer, and is known as the MVME187Bug, or just 187Bug.

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Page 83

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Motorola Debugger General Information, Introduction to MVME187Bug, Overview of M88000 Firmware, This Chapter Covers

Contents

MVME187IG/D4 MVME187 RISC Single Board Computer Installation GuideRestricted Rights Legend Preface Dangerous Procedure Warnings Safety Summary Safety Depends On YouDo Not Service or Adjust Alone Use Caution When Exposing or Handling the CRTThis equipment generates, uses, and can radiate electro Page Contents Battery Backed Up RAM and Clock VMEbus Interface I/O Interfaces Front Panel Switches and LEDs Data Bus StructureLocal Bus Arbitration M88000 MPU EPROM Programmable EPROM Features Static RAM Optional SRAM Battery Backup Onboard DRAMPowering Up the System 3-25 Initializing the Real-Time Clock Jumper Settings Optional Jumper SettingsInstalling the Hardware Installing the MVME187 in the Chassis Completing the Installation 3-24 Starting the SystemBO Bootstrap Operating System 4-15 BH Bootstrap and Halt Booting and Restarting 187Bug 4-5 Starting Up 187Bug 4-6 AutobootAutoboot Sequence 4-6 ROMboot ROMboot Sequence 4-7 Network Boot Network Boot Sequence 4-8 Restarting the System Reset Abort BreakMPCR Status Codes Multiprocessor Address Register MPAR 4-22 MPCR Powerup Sequence187Bug Diagnostic Test Groups 4-27 This Chapter Covers The 187Bug Debugger Command Set 5-15 This Appendix Covers A-1Signal Adaptations E-4 Sample ConÞgurations E-4 Proper Grounding E-7 Typical Transition Module Peripheral Port Connectors List of FiguresMVME187 General Block Diagram Using MVME712A/AM and MVME712BList of Tables About this Manual 1Introduction to the MVME187 Installation GuideThis Chapter Covers Data and Address Parameter Numeric Formats Signal Name ConventionsTerminology, Conventions, and Deﬁnitions Used in this Manual Big-Endian Byte Ordering Assertion and Negation ConventionsData and Address Size Deﬁnitions The bit can be set and cleared under software Control and Status Bit DeﬁnitionsTrue/False Bit State Deﬁnitions Bit Value DescriptionsDocument Set for MVME187-0xx Board Related DocumentationAlso available but not included in the set Additional Manuals for this BoardOther Applicable Motorola Publications Non-Motorola Peripheral Controllers Publications Bundle Part Number Introduction to the MVME187 Installation GuideData Sheet MC68230 Parallel Interface Timer PI/T Data SheetSheet, order number Applicable Non-Motorola PublicationsANSI/IEEE Std Data, IEC 821 BUS1-10 Introduction to the MVME187 Installation GuideThis Chapter Covers Board Level Hardware DescriptionGeneral Description SCSI Mass Storage Interface Onboard Memory Mezzanine ModuleEthernet Transceiver Interface Serial PortsParallel Printer Port 187Bug Firmware FeaturesFour 32-bit tick timers for periodic interrupts Watchdog timer Table 2-1. MVME187 General Speciﬁcations SpeciﬁcationsConformance to Requirements Adapters ConnectorsFigure 2-1. MVME187 General Block Diagram Board Level OverviewASICs Transition ModulesPCCchip2 ASIC VMEchip2 ASICTable 2-2. Bus Transfers MCECC Memory Controller ASIC Functional DescriptionMEMC040 Memory Controller ASIC Table 2-4. Front Panel LEDs Front Panel Switches and LEDsTable 2-3. Front Panel Switches Local Bus Arbitration Data Bus StructureM88000 MPU Static RAM Programmable EPROM FeaturesEPROM Optional SRAM Battery Backup Onboard DRAM DRAM Programming Considerations Stacking MezzaninesBattery Backed Up RAM and Clock Serial Port Interface VMEbus InterfaceI/O Interfaces Serial Interface Programming Considerations Parallel Port Interface Ethernet Interface SCSI Termination Buffer OverrunsSCSI Interface Local Resources Programmable Tick TimersWatchdog Timer Local Bus TimeoutNormal Address Range Devices Memory MapsLocal Bus Memory Map Table 2-5. Local Bus Memory Map Table 2-6. Local I/O Devices Memory Map Table 2-6. Local I/O Devices Memory Map Continued VMEbus Short I/O Memory Map VMEbus Accesses to the Local BusVMEbus Memory Map This Chapter Covers Hardware Preparation and InstallationUnpacking the Equipment Table 3-1. Startup Overview Overview of Startup ProcedureUserÕs Manual Table 3-1. Startup Overview Continuedobtain the Single Board Computer SCSI Softwareobtain the Debugging Table 3-1. Startup Overview Continuedpage Option Modiﬁcation Modifying Conﬁguration before InstallationPreparing the Hardware MVME Figure 3-1. MVME187 Switches, Headers, Connectors, Fuses, and LEDsEPROM Orientation Jumper SettingsChecking the 187Bug EPROMs EPROM LocationReserved/DeÞned Bits Optional Jumper SettingsGeneral Purpose Software Readable Header J1 GPI4 - GPI7 Table 3-3. Factory Settings for J1 General Purpose Readable JumpersTable 3-2. J1 Bit Descriptions GPI0 - GPI3System Table 3-4. Settings for J2 System Controller HeaderSystem Controller Header J2 Serial Port 4 Clock Conﬁguration Select Headers J7 and J8 Optional SRAM Backup Power Source Select Header J6Select Header Table 3-5. Settings for Optional J6 SRAM Backup Power Sourceclock Table 3-6. Settings for J7 and J8 Serial Port 4 Clock ConﬁgurationSelect Headers Serial PortTable 3-7. MVME187 Preparation Procedure Preparing the MVME187 for InstallationPreparing the System Chassis Table 3-8. Chassis Preparation/Slot Selection ProcedureTable 3-9. MVME187 Installation Procedure Installing the HardwareInstalling the MVME187 in the Chassis 3-17 Transition Modules and Adapter Boards OverviewInstalling the Hardware 3-18 Figure 3-2. Typical Internal SCSI and Serial Port ConnectionsHardware Preparation and Installation External SCSI drives Equipment ConnectionsTable 3-10. Peripheral Connections Some connection diagrams are in the Single Board ComputerTable 3-11. Transition Module and Adapter Board Installation Overview Installing Transition Modules and Adapter BoardsConnecting Peripherals powerup Table 3-12. Peripheral Connection Proceduresparity disabled no parity baud rate 9600 baud default baud rate of MVME187 ports atFigure 3-3. Using MVME712A/AM and MVME712B To J10 on Figure 3-4. Typical Transition Module Peripheral Port ConnectorsMVME 712ATable 3-14. System Startup Overview Completing the InstallationTable 3-13. Installation Completion Procedure Starting the SystemBoard Mode Powering Up the SystemInitializing the Real-Time Clock Examining and/or Changing Environmental Parameters187-BugSET 0522961037 Return Table 3-15. RTC Initialization ProcedureProgramming the PCCchip2 and VMEchip2 SET MMddyyhhmm+/-CALCMemory Address Ranges Backplane Power ConnectionsGlobal Bus Timeout System ConsiderationsEthernet LAN +12 Vdc Fuse Multiple Module Cage ConﬁgurationGCSR Location Monitor Register 187-Bugps Return SCSI Bus TerminationStorage and the Real-Time Clock 3-30 Hardware Preparation and InstallationThis Chapter Covers Debugger General InformationIntroduction to MVME187Bug Overview of M88000 FirmwareTrap #496 Routines Command FacilitiesDescription of 187Bug Keyboard Control Debugger or Diagnostic Directories187Bug Implementation Comparison with M68000-Based FirmwareMemory Requirements Booting and Restarting 187BugStarting Up 187Bug AutobootAutoboot Sequence ROMboot Sequence ROMbootNetwork Boot Sequence Network BootRestarting the System Abort ResetDuring COLD reset During WARM resetBreak Abort SequenceMPU Clock Speed Calculation Break SequenceSYSFAIL* Assertion/Negation Supported Controllers Disk I/O SupportDisk Support Facilities Parameter TablesDevice Probe Function Blocks Versus SectorsIOP Physical I/O to Disk Disk I/O via 187Bug CommandsBO Bootstrap Operating System IOI Input/Output InquiryDisk I/O via 187Bug System Calls BH Bootstrap and HaltController Command Packets Default 187Bug Controller and Device Parameters source Disk I/O Error CodesUDP/IP Protocol Modules Network I/O SupportIntel 82596 LAN Coprocessor Ethernet Driver TFTP Protocol Module BOOTP Protocol ModuleNetwork Boot Control Module RARP/ARP Protocol ModulesMultiprocessor Control Register MPCR Method Network I/O Error CodesMultiprocessor Support Multiprocessor Address Register MPAR MPCR Powerup SequenceMPCR Status Codes 3. As the initialization proceeds, the execution path comes to the prompt routine Global Control and Status Register GCSR Method Table 4-1. Diagnostic Monitor Commands/Preﬁxes Diagnostic FacilitiesCommand Table 4-2. Diagnostic UtilitiesTable 4-1. Diagnostic Monitor Commands/Preﬁxes CommandTable 4-3. Diagnostic Test Groups 187Bug Diagnostic Test Groups4-28 Debugger General InformationThis Chapter Covers Using the 187Bug DebuggerEntering Debugger Command Lines Terminal Input/Output ControlUsing the 187Bug Debugger Debugger Command Syntax Expression as a Parameter Syntactic VariablesAddress as a Parameter Address Formats Offset Registers Port NumbersDownloading an S-Record Object File Entering and Debugging ProgramsCreating a Program with the Assembler/Disassembler Read the Program from Disk Calling System Utilities from User Programs187Bug Vector Table and Workspace Preserving the Debugger Operating EnvironmentCPU/MPU Registers Floating Point SupportHardware Functions Exception Vectors Used by 187Bug1. The sign field is the first field and is a binary field 3 hex digits. Bias = $3FF Single Precision RealDouble Precision Real 2 hex digits. Bias = $7FScientiﬁc Notation BC range del addr B H W The 187Bug Debugger Command SetTable 5-1. Debugger Commands AS addrDS addr count del addr Table 5-1. Debugger Commands ContinuedHE command DMA range del addr del vdir del am del blkMAR controller LUN del device LUN Table 5-1. Debugger Commands ContinuedMAW controller LUN del device LUN del block #SET mmddyyhhmm n C Table 5-1. Debugger Commands ContinuedSYMS symbol-name S RS reg del exp del addr S DConﬁguring the Board Information Block AConﬁgure and Environment CommandsThis Appendix Covers Page ENV D Setting Environment to Bug/Operating SystemThe parameters to be configured are listed in the following table Table A-1. ENV Command ParametersFFBFFFFC Table A-1. ENV Command Parameters ContinuedTable A-1. ENV Command Parameters Continued Table A-1. ENV Command Parameters Continued FFFFCE0F Table A-1. ENV Command Parameters Continued01FFFFFF Table A-1. ENV Command Parameters ContinuedFFE1FFFF Table A-1. ENV Command Parameters ContinuedGuide 01FFEFFFFFFF Table A-1. ENV Command Parameters ContinuedTable A-1. ENV Command Parameters Continued Table A-1. ENV Command Parameters Continued A-14 Configure and Environment CommandsDisk/Tape Controller Modules Supported BDisk/Tape Controller Data$XXXXXXXX Disk/Tape Controller Default ConﬁgurationsMVME328 -- 14 Devices MVME327A -- 9 DevicesMVME350 -- 1 Device IOT Command Parameters for Supported Floppy TypesDSDD5 Other CharacteristicsIOT Parameter Floppy Types and FormatsDisk/Tape Controller Data Network Controller Modules Supported Table C-1. Network Controller Access DataCNetwork Controller Data Table C-1. Network Controller Access Data Continued Table D-1. Troubleshooting Steps DTroubleshooting the MVME187 Solving Startup ProblemsTable D-1. Troubleshooting Steps Continued III. Debug Table D-1. Troubleshooting Steps ContinuedBREAK Table D-1. Troubleshooting Steps Continued3. When prompted to Update Non-Volatile RAM, type in 187-DiagTable D-1. Troubleshooting Steps Continued Troubleshooting the MVME187 Solving Startup Problems Introduction EEIA-232-D InterconnectionsGrounding Table E-1. EIA-232-D InterconnectionsTable E-1. EIA-232-D Interconnections Continued Levels of ImplementationSample Conﬁgurations Signal AdaptationsFigure E-1. Middle-of-the-Road EIA-232-D Conﬁguration Figure E-2. Minimum EIA-232-D Connection Proper Grounding EIA-232-D Interconnections Numerics SymbolsIndex I N D E I N D E error codessupport via 187Bug commands 4-15 via 187Bug system calls default configurations B-2I N D E I N D E local bus local I/O devices 2-26 VMEbus 2-28 VMEbus short I/OI N D E see also CD2401 scientific notation 5-14 SCON LED I N D Esee also CD2401 serial port 1 5-8 serial port 2 in NVRAMedge significant 1-2 level significant I N D EI N D E