Levels of Implementation | Motorola MVME187 guide

			Levels of Implementation
		Table E-1. EIA-232-D Interconnections (Continued)

	Pin	Signal	Signal Name and Description
	Number	Mnemonic	Signal Name and Description
	Number	Mnemonic

	22	RI	RING INDICATOR. Output from the modem to the terminal;
			indicates to the terminal that an incoming call is present. The
			terminal causes the modem to answer the phone by carrying
			DTR true while RI is active.

	23		Not used.

	24	TxC	TRANSMIT CLOCK (DTE). Input to modem from terminal;
			same function as TxC on pin 15.

	25	BSY	BUSY. Input to modem from terminal. A positive EIA signal
			applied to this pin causes the modem to go off-hook and make
			the associated phone busy.

Levels of Implementation

There are several levels of conformance that may be appropriate for typical EIA-232-D interconnections. The bare minimum requirement is the two data lines and a ground. The full implementation of EIA-232-D requires 12 lines; it accommodates:

❏Automatic dialing

❏Automatic answering

❏Synchronous transmission

A middle-of-the-road approach is illustrated in Figure E-1.

E

E-3

Image 159

Motorola MVME187 manual Levels of Implementation, Signal Name and Description Number Mnemonic

Contents

MVME187 Risc Single Board Computer Installation Guide Restricted Rights Legend Preface Assembly Item Board Description Safety Summary Safety Depends On You Copyright Motorola All Rights Reserved March Page Contents Page Page Page Page Page List of Figures List of Tables About this Manual This Chapter Covers Data and Address Parameter Numeric Formats Signal Name Conventions Assertion and Negation Conventions Data and Address Size DeﬁnitionsBig-Endian Byte Ordering Control and Status Bit Deﬁnitions True/False Bit State DeﬁnitionsBit Value Descriptions Related Documentation Document Set for MVME187-0xxBoardMotorola Description Publication Number Motorola Description Additional Manuals for this BoardOther Applicable Motorola Publications Single Board Computers Scsi Software UserÕs Manual Part Number Description Non-Motorola Peripheral Controllers Publications Bundle SBCCOMPS/L Document Title Source Applicable Non-Motorola Publications Introduction to the MVME187 Installation Guide General Description Board Level Hardware Description Scsi Mass Storage Interface Onboard Memory Mezzanine Module Ethernet Transceiver Interface Serial Function Synchronous Signals Bit RatesSerial Ports Parallel Printer Port 187Bug Firmware Features Features MVME187 General Speciﬁcations Characteristics SpeciÞcationsSpeciﬁcations Conformance to Requirements Connectors Board Level OverviewAdapters ASICs Transition Modules Transfer type Can be VMEchip2 AsicBus Transfers PCCchip2 Asic Functional Description MEMC040 Memory Controller AsicMcecc Memory Controller Asic Front Panel LEDs Front Panel Switches and LEDsFront Panel Switches Switch Description Data Bus Structure M88000 MPULocal Bus Arbitration Static RAM Programmable Eprom Features See Optional Sram Backup Power Source Select Header J6 on Optional Sram Battery Backup Onboard Dram Dram Programming Considerations Stacking Mezzanines Battery Backed Up RAM and Clock VMEbus Interface InterfacesSerial Port Interface Serial Interface Programming Considerations Status Pins Control PinsParallel Port Interface Ethernet Interface Scsi Interface Buffer Overruns Local Resources Programmable Tick TimersWatchdog Timer Local Bus Timeout Memory Maps Local Bus Memory MapNormal Address Range Devices Inhibit Address Software Devices Accessed Port SizeLocal Bus Memory Map Range Local I/O Devices Memory Map Address Range Devices Accessed Port Size $FFFE000B Iack Level VMEbus Accesses to the Local Bus VMEbus Memory MapVMEbus Short I/O Memory Map Unpacking the Equipment Hardware Preparation and Installation Stage What you will need to do Refer to Prepare the MVME187 Overview of Startup ProcedureInstall your MVME187 in the chassis Startup Overview Complete the installation Stage What you will need to do Refer toConnect peripherals Package for Motorola 88K Modifying Conﬁguration before Installation Preparing the HardwareOption Modiﬁcation MVME187 Switches, Headers, Connectors, Fuses, and LEDs Eprom Orientation Jumper SettingsChecking the 187Bug EPROMs Eprom Location General Purpose Software Readable Header J1 Optional Jumper Settings Header ConÞguration Jumpers Number Description Factory Settings for J1 General Purpose Readable JumpersBit J1 Pins Description J1 Bit Descriptions System Controller Header J2 Settings for J2 System Controller Header Serial Port 4 Clock Conﬁguration Select Headers J7 and J8 Optional Sram Backup Power Source Select Header J6 Primary source VMEbus Number Description Preparing the MVME187 for Installation MVME187 Preparation ProcedureAction Chassis Preparation/Slot Selection Procedure Preparing the System ChassisStep Action Installing the Hardware Installing the MVME187 in the ChassisMVME187 Installation Procedure Transition Modules and Adapter Boards Overview Typical Internal Scsi and Serial Port Connections Equipment Connections 10. Peripheral ConnectionsEquipment Type Connect Through Connecting Peripherals Installing Transition Modules and Adapter Boards Action Refer to 12. Peripheral Connection Procedures Using MVME712A/AM and MVME712B Typical Transition Module Peripheral Port Connectors 14. System Startup Overview Completing the Installation13. Installation Completion Procedure Starting the System Initializing the Real-Time Clock Powering Up the SystemIf 187Bug is Board Mode System Mode 15. RTC Initialization Procedure Step Action Board Mode System ModeProgramming the PCCchip2 and VMEchip2 Memory Address Ranges Backplane Power ConnectionsGlobal Bus Timeout System Considerations Multiple Module Cage Conﬁguration Gcsr Location Monitor RegisterEthernet LAN +12 Vdc Fuse Storage and the Real-Time Clock Scsi Bus Termination Hardware Preparation and Installation Overview of M88000 Firmware Introduction to MVME187Bug Command Facilities Description of 187BugTrap #496 Routines Keyboard Control Debugger or Diagnostic Directories 187Bug Implementation Comparison with M68000-Based Firmware Memory Requirements Booting and Restarting 187Bug Autoboot Autoboot SequenceStarting Up 187Bug ROMboot Sequence ROMboot Network Boot Network Boot SequenceRequirement Optionally, with the ENV command Restarting the System Abort Reset Break Abort Sequence MPU Clock Speed Calculation SYSFAIL* Assertion/Negation Supported Controllers Disk I/O SupportDisk Support Facilities Parameter Tables Device Probe Function Blocks Versus Sectors Disk I/O via 187Bug Commands BH Bootstrap and Halt Controller Command PacketsDisk I/O via 187Bug System Calls Default 187Bug Controller and Device Parameters BO or BH Disk I/O Error CodesUsing When you invoke one Change These commands Status is Command Network I/O Support Intel 82596 LAN Coprocessor Ethernet DriverUDP/IP Protocol Modules Tftp Protocol Module Bootp Protocol ModuleNetwork Boot Control Module RARP/ARP Protocol Modules Network I/O Error Codes Multiprocessor SupportMultiprocessor Control Register Mpcr Method Mpcr Powerup Sequence Mpcr Status CodesMultiprocessor Address Register Mpar Multiprocessor Support Global Control and Status Register Gcsr Method Diagnostic Facilities Diagnostic Monitor Commands/PreﬁxesCommand Description PreÞx Command Description Write loop enable Read loop enable Diagnostic Utilities Diagnostic Test Groups 187Bug Diagnostic Test Groups Debugger General Information Terminal Input/Output Control Entering Debugger Command Lines More characters to it. You can edit the line by Debugger Command Syntax Syntactic Variables Expression as a ParameterBase IdentiÞer Examples Address as a Parameter String Numeric Value LiteralExpression Result In Hex Address Formats Offset Registers Port Numbers Entering and Debugging Programs Creating a Program with the Assembler/DisassemblerDownloading an S-Record Object File Read the Program from Disk Calling System Utilities from User Programs 187Bug Vector Table and Workspace Preserving the Debugger Operating Environment CPU/MPU Registers Floating Point SupportHardware Functions Exception Vectors Used by 187Bug Floating Point Data Types Integer Data Types Double Precision Real Single Precision Real Scientiﬁc Notation Debugger Commands 187Bug Debugger Command Set IOI C L Cnfg I MCS range B H W ENV D Nopf port Niot HAZn a Nopa port VER E RL addr B H WSYM addr Time C L O This Appendix Covers Conﬁguring the Board Information BlockCnfg IM Configure and Environment Commands Setting Environment to Bug/Operating System ENV Parameter and Options Default Meaning of Default Table A-1. ENV Command Parameters First location tested when the Bug LUN Network Auto Boot ConÞguration Memory Search Ending Address Slave address decoders setup Guide Base address of the VMEbus resource This will be the local bus address Table A-1. ENV Command Parameters Configure and Environment Commands Disk/Tape Controller Modules Supported Controller Type First SecondAddress $XXXXXXXX Disk/Tape Controller Default Conﬁgurations Controller LUN Address Device LUN Device Type MVME327A -- 9 Devices IOT Parameter Floppy Types and Formats IOT Command Parameters for Supported Floppy Types Other Characteristics Disk/Tape Controller Data Address Interface Table C-1. Network Controller Access DataDebugger Commands Debugger System Calls Network Controller Modules Supported $FFFFA400 Condition Possible Try This Problem Table D-1. Troubleshooting Steps Troubleshooting the MVME187 Solving Startup Problems Table D-1. Troubleshooting Steps Set mmddyyhhmm Return Envd ReturnReturn Env Return St ReturnDe Return Troubleshooting the MVME187 Solving Startup Problems Introduction EEIA-232-D Interconnections Number Mnemonic Signal Name and DescriptionTable E-1. EIA-232-D Interconnections Pin Levels of Implementation Signal Name and Description Number Mnemonic Sample Conﬁgurations Signal Adaptations Figure E-1. Middle-of-the-Road EIA-232-D Conﬁguration Figure E-2. Minimum EIA-232-D Connection Proper Grounding EIA-232-D Interconnections Index Bootp Default configurations B-2 IN-12 Local bus Local I/O devices 2-26VMEbus 2-28VMEbus short I/O IN-14 See also CD2401 scientific notation 5-14 Scon LED Nvram XON/XOFF