Motorola MVME187 manual Local Bus Memory Map, Address Software Devices Accessed Port Size, Range

Memory Maps

Table 2-5. Local Bus Memory Map

Address				Software
	Devices Accessed	Port Size	Size	Cache	Notes
Range
				Inhibit
$00000000 -	User programmable	D32	DRAMSIZE	N	1, 2
DRAMSIZE	(onboard DRAM)
DRAMSIZE	User programmable	D32/D16	3GB	?	3, 4
- $FF7FFFFF	(VMEbus)
$FF800000 -	ROM	D32	4MB	N	1
$FFBFFFFF
$FFC00000 -	Reserved	--	2MB	--	5
$FFDFFFFF
$FFE00000 -	SRAM	D32	128KB	N	--
$FFE1FFFF
$FFE20000 -	SRAM (repeated)	D32	896KB	N	--
$FFEFFFFF
$FFF00000 -	Local I/O devices	D32-D8	1MB	Y	3
$FFFEFFFF	(refer to next table)
$FFFF0000 -	User programmable	D32/D16	64KB	?	2, 4
$FFFFFFFF	(VMEbus A16)

Notes

1.Onboard EPROM appears at $00000000 - $003FFFFF following a local bus reset. The EPROM appears at 0 until the ROM0 bit is cleared in the VMEchip2. The ROM0 bit is located at address $FFF40030 bit 20. The EPROM must be disabled at 0 before the DRAM is enabled. The VMEchip2 and DRAM map decoders are disabled by a local bus reset.

2.This area is user-programmable. The suggested use is shown in the table. The DRAM decoder is programmed in the MEMC040 or MCECC chip, and the local-to-VMEbus decoders are programmed in the VMEchip2.

3.Size is approximate.

4.Cache inhibit depends on devices in area mapped.

5.This area is not decoded. If these locations are accessed and the local bus timer is enabled, the cycle times out and is terminated by a TEA signal.

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