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Motorola MVME187 VMEbus Memory Map, VMEbus Accesses to the Local Bus, VMEbus Short I/O Memory Map

Models: MVME187

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VMEbus Memory Map

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Board Level Hardware Description

VMEbus Memory Map

This section describes the mapping of local resources as viewed by VMEbus masters. Default addresses for the slave, master, and GCSR address decoders are provided by the ENV command. Refer to Appendix A.

VMEbus Accesses to the Local Bus

The VMEchip2 includes a user-programmable map decoder for the VMEbus to local bus interface. The map decoder allows you to program the starting and ending address and the modifiers the MVME187 responds to.

VMEbus Short I/O Memory Map

The VMEchip2 includes a user-programmable map decoder for the GCSR. The GCSR map decoder allows you to program the starting address of the GCSR in the VMEbus short I/O space.

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Motorola MVME187 manual VMEbus Memory Map, VMEbus Accesses to the Local Bus, VMEbus Short I/O Memory Map

Contents

MVME187 RISC Single Board Computer Installation Guide MVME187IG/D4Restricted Rights Legend Preface Safety Summary Safety Depends On You Do Not Service or Adjust AloneUse Caution When Exposing or Handling the CRT Dangerous Procedure WarningsThis equipment generates, uses, and can radiate electro Page Contents Front Panel Switches and LEDs Data Bus Structure Local Bus Arbitration M88000 MPU EPROM Programmable EPROM FeaturesStatic RAM Optional SRAM Battery Backup Onboard DRAM Battery Backed Up RAM and Clock VMEbus Interface I/O InterfacesJumper Settings Optional Jumper Settings Installing the Hardware Installing the MVME187 in the ChassisCompleting the Installation 3-24 Starting the System Powering Up the System 3-25 Initializing the Real-Time ClockBooting and Restarting 187Bug 4-5 Starting Up 187Bug 4-6 Autoboot Autoboot Sequence 4-6 ROMboot ROMboot Sequence 4-7 Network BootNetwork Boot Sequence 4-8 Restarting the System Reset Abort Break BO Bootstrap Operating System 4-15 BH Bootstrap and HaltMultiprocessor Address Register MPAR 4-22 MPCR Powerup Sequence 187Bug Diagnostic Test Groups 4-27 This Chapter CoversThe 187Bug Debugger Command Set 5-15 This Appendix Covers A-1 MPCR Status CodesSignal Adaptations E-4 Sample ConÞgurations E-4 Proper Grounding E-7 List of Figures MVME187 General Block DiagramUsing MVME712A/AM and MVME712B Typical Transition Module Peripheral Port ConnectorsList of Tables This Chapter Covers 1Introduction to the MVME187 Installation GuideAbout this Manual Terminology, Conventions, and Deﬁnitions Used in this Manual Signal Name ConventionsData and Address Parameter Numeric Formats Data and Address Size Deﬁnitions Assertion and Negation ConventionsBig-Endian Byte Ordering Control and Status Bit Deﬁnitions True/False Bit State DeﬁnitionsBit Value Descriptions The bit can be set and cleared under softwareRelated Documentation Document Set for MVME187-0xx BoardOther Applicable Motorola Publications Additional Manuals for this BoardAlso available but not included in the set Non-Motorola Peripheral Controllers Publications Bundle Introduction to the MVME187 Installation Guide Data SheetMC68230 Parallel Interface Timer PI/T Data Sheet Part NumberApplicable Non-Motorola Publications ANSI/IEEE StdData, IEC 821 BUS Sheet, order numberIntroduction to the MVME187 Installation Guide 1-10General Description Board Level Hardware DescriptionThis Chapter Covers Onboard Memory Mezzanine Module SCSI Mass Storage InterfaceParallel Printer Port Serial PortsEthernet Transceiver Interface Features 187Bug FirmwareFour 32-bit tick timers for periodic interrupts Watchdog timer Conformance to Requirements SpeciﬁcationsTable 2-1. MVME187 General Speciﬁcations Connectors Figure 2-1. MVME187 General Block DiagramBoard Level Overview AdaptersTransition Modules ASICsTable 2-2. Bus Transfers VMEchip2 ASICPCCchip2 ASIC MEMC040 Memory Controller ASIC Functional DescriptionMCECC Memory Controller ASIC Table 2-3. Front Panel Switches Front Panel Switches and LEDsTable 2-4. Front Panel LEDs M88000 MPU Data Bus StructureLocal Bus Arbitration EPROM Programmable EPROM FeaturesStatic RAM Optional SRAM Battery Backup Onboard DRAM Stacking Mezzanines DRAM Programming ConsiderationsBattery Backed Up RAM and Clock I/O Interfaces VMEbus InterfaceSerial Port Interface Serial Interface Programming Considerations Parallel Port Interface Ethernet Interface SCSI Interface Buffer OverrunsSCSI Termination Programmable Tick Timers Watchdog TimerLocal Bus Timeout Local ResourcesLocal Bus Memory Map Memory MapsNormal Address Range Devices Table 2-5. Local Bus Memory Map Table 2-6. Local I/O Devices Memory Map Table 2-6. Local I/O Devices Memory Map Continued VMEbus Memory Map VMEbus Accesses to the Local BusVMEbus Short I/O Memory Map Unpacking the Equipment Hardware Preparation and InstallationThis Chapter Covers Overview of Startup Procedure Table 3-1. Startup OverviewTable 3-1. Startup Overview Continued obtain the Single BoardComputer SCSI Software UserÕs Manualpage Table 3-1. Startup Overview Continuedobtain the Debugging Preparing the Hardware Modifying Conﬁguration before InstallationOption Modiﬁcation Figure 3-1. MVME187 Switches, Headers, Connectors, Fuses, and LEDs MVMEJumper Settings Checking the 187Bug EPROMsEPROM Location EPROM OrientationGeneral Purpose Software Readable Header J1 Optional Jumper SettingsReserved/DeÞned Bits Table 3-3. Factory Settings for J1 General Purpose Readable Jumpers Table 3-2. J1 Bit DescriptionsGPI0 - GPI3 GPI4 - GPI7System Controller Header J2 Table 3-4. Settings for J2 System Controller HeaderSystem Optional SRAM Backup Power Source Select Header J6 Serial Port 4 Clock Conﬁguration Select Headers J7 and J8Table 3-5. Settings for Optional J6 SRAM Backup Power Source Select HeaderTable 3-6. Settings for J7 and J8 Serial Port 4 Clock Conﬁguration Select HeadersSerial Port clockPreparing the MVME187 for Installation Table 3-7. MVME187 Preparation ProcedureTable 3-8. Chassis Preparation/Slot Selection Procedure Preparing the System ChassisInstalling the MVME187 in the Chassis Installing the HardwareTable 3-9. MVME187 Installation Procedure Installing the Hardware Transition Modules and Adapter Boards Overview3-17 Hardware Preparation and Installation Figure 3-2. Typical Internal SCSI and Serial Port Connections3-18 Equipment Connections Table 3-10. Peripheral ConnectionsSome connection diagrams are in the Single Board Computer External SCSI drivesConnecting Peripherals Installing Transition Modules and Adapter BoardsTable 3-11. Transition Module and Adapter Board Installation Overview Table 3-12. Peripheral Connection Procedures parity disabled no paritybaud rate 9600 baud default baud rate of MVME187 ports at powerupFigure 3-3. Using MVME712A/AM and MVME712B Figure 3-4. Typical Transition Module Peripheral Port Connectors MVME712A To J10 onCompleting the Installation Table 3-13. Installation Completion ProcedureStarting the System Table 3-14. System Startup OverviewPowering Up the System Initializing the Real-Time ClockExamining and/or Changing Environmental Parameters Board ModeTable 3-15. RTC Initialization Procedure Programming the PCCchip2 and VMEchip2SET MMddyyhhmm+/-CALC 187-BugSET 0522961037 ReturnBackplane Power Connections Global Bus TimeoutSystem Considerations Memory Address RangesGCSR Location Monitor Register Multiple Module Cage ConﬁgurationEthernet LAN +12 Vdc Fuse Storage and the Real-Time Clock SCSI Bus Termination187-Bugps Return Hardware Preparation and Installation 3-30Debugger General Information Introduction to MVME187BugOverview of M88000 Firmware This Chapter CoversDescription of 187Bug Command FacilitiesTrap #496 Routines Debugger or Diagnostic Directories Keyboard ControlComparison with M68000-Based Firmware 187Bug ImplementationBooting and Restarting 187Bug Memory RequirementsAutoboot Sequence AutobootStarting Up 187Bug ROMboot ROMboot SequenceNetwork Boot Network Boot SequenceRestarting the System Reset During COLD resetDuring WARM reset AbortAbort Sequence BreakSYSFAIL* Assertion/Negation Break SequenceMPU Clock Speed Calculation Disk I/O Support Disk Support FacilitiesParameter Tables Supported ControllersBlocks Versus Sectors Device Probe FunctionDisk I/O via 187Bug Commands BO Bootstrap Operating SystemIOI Input/Output Inquiry IOP Physical I/O to DiskController Command Packets BH Bootstrap and HaltDisk I/O via 187Bug System Calls Default 187Bug Controller and Device Parameters Disk I/O Error Codes sourceIntel 82596 LAN Coprocessor Ethernet Driver Network I/O SupportUDP/IP Protocol Modules BOOTP Protocol Module Network Boot Control ModuleRARP/ARP Protocol Modules TFTP Protocol ModuleMultiprocessor Support Network I/O Error CodesMultiprocessor Control Register MPCR Method MPCR Status Codes MPCR Powerup SequenceMultiprocessor Address Register MPAR 3. As the initialization proceeds, the execution path comes to the prompt routine Global Control and Status Register GCSR Method Diagnostic Facilities Table 4-1. Diagnostic Monitor Commands/PreﬁxesTable 4-2. Diagnostic Utilities Table 4-1. Diagnostic Monitor Commands/PreﬁxesCommand Command187Bug Diagnostic Test Groups Table 4-3. Diagnostic Test GroupsDebugger General Information 4-28Using the 187Bug Debugger Entering Debugger Command LinesTerminal Input/Output Control This Chapter CoversUsing the 187Bug Debugger Debugger Command Syntax Syntactic Variables Expression as a ParameterAddress as a Parameter Address Formats Port Numbers Offset RegistersCreating a Program with the Assembler/Disassembler Entering and Debugging ProgramsDownloading an S-Record Object File Calling System Utilities from User Programs Read the Program from DiskPreserving the Debugger Operating Environment 187Bug Vector Table and WorkspaceFloating Point Support Hardware FunctionsException Vectors Used by 187Bug CPU/MPU Registers1. The sign field is the first field and is a binary field Single Precision Real Double Precision Real2 hex digits. Bias = $7F 3 hex digits. Bias = $3FFScientiﬁc Notation The 187Bug Debugger Command Set Table 5-1. Debugger CommandsAS addr BC range del addr B H WTable 5-1. Debugger Commands Continued HE commandDMA range del addr del vdir del am del blk DS addr count del addrTable 5-1. Debugger Commands Continued MAW controller LUNdel device LUN del block # MAR controller LUN del device LUNTable 5-1. Debugger Commands Continued SYMS symbol-name SRS reg del exp del addr S D SET mmddyyhhmm n CThis Appendix Covers AConﬁgure and Environment CommandsConﬁguring the Board Information Block Page Setting Environment to Bug/Operating System ENV DTable A-1. ENV Command Parameters The parameters to be configured are listed in the following tableTable A-1. ENV Command Parameters Continued FFBFFFFCTable A-1. ENV Command Parameters Continued Table A-1. ENV Command Parameters Continued Table A-1. ENV Command Parameters Continued FFFFCE0FTable A-1. ENV Command Parameters Continued 01FFFFFFTable A-1. ENV Command Parameters Continued Guide01FF FFE1FFFFTable A-1. ENV Command Parameters Continued EFFFFFFFTable A-1. ENV Command Parameters Continued Table A-1. ENV Command Parameters Continued Configure and Environment Commands A-14BDisk/Tape Controller Data Disk/Tape Controller Modules SupportedDisk/Tape Controller Default Conﬁgurations $XXXXXXXXMVME327A -- 9 Devices MVME328 -- 14 DevicesIOT Command Parameters for Supported Floppy Types MVME350 -- 1 DeviceOther Characteristics IOT ParameterFloppy Types and Formats DSDD5Disk/Tape Controller Data CNetwork Controller Data Table C-1. Network Controller Access DataNetwork Controller Modules Supported Table C-1. Network Controller Access Data Continued DTroubleshooting the MVME187 Solving Startup Problems Table D-1. Troubleshooting StepsTable D-1. Troubleshooting Steps Continued Table D-1. Troubleshooting Steps Continued III. DebugTable D-1. Troubleshooting Steps Continued 3. When prompted to Update Non-Volatile RAM, type in187-Diag BREAKTable D-1. Troubleshooting Steps Continued Troubleshooting the MVME187 Solving Startup Problems EEIA-232-D Interconnections IntroductionTable E-1. EIA-232-D Interconnections GroundingLevels of Implementation Table E-1. EIA-232-D Interconnections ContinuedSignal Adaptations Sample ConﬁgurationsFigure E-1. Middle-of-the-Road EIA-232-D Conﬁguration Figure E-2. Minimum EIA-232-D Connection Proper Grounding EIA-232-D Interconnections Index SymbolsNumerics I N D E error codes support via 187Bug commands 4-15 via 187Bug system callsdefault configurations B-2 I N D EI N D E local bus local I/O devices 2-26 VMEbus 2-28 VMEbus short I/O I N D EI N D E I N D E see also CD2401 scientific notation 5-14 SCON LEDin NVRAM edge significant 1-2 level significantI N D E see also CD2401 serial port 1 5-8 serial port 2I N D E