Speciﬁcations, Conformance to Requirements | Motorola MVME187

2

Board Level Hardware Description

Speciﬁcations

Table 2-1. MVME187 General Speciﬁcations

	Characteristics			SpeciÞcations

	Power requirements		+5 Vdc (+/-5%)	3.5 A (typical), 4.5 A (maximum)
	(with all four EPROM sockets			(at 25 MHz, with 32MB parity DRAM)
	populated and excluding
	populated and excluding			5.0 A (typical), 6.5 A (maximum)
	external LAN transceiver)			5.0 A (typical), 6.5 A (maximum)
	external LAN transceiver)			(at 33 MHz, with 128MB ECC DRAM)
				(at 33 MHz, with 128MB ECC DRAM)

			+12 Vdc (+/-5%)	100 mA (maximum)
				(1.0 A (maximum) with offboard LAN
				transceiver)

			-12 Vdc (+/- 5%)	100 mA (maximum)

	Operating temperature		0û to 55û C at point of entry of forced air
			(approximately 490 LFM)

	Storage temperature		-40û to +85û C

	Relative humidity		5% to 90% (non-condensing)

	Physical	PC board with	Height	9.187 inches (233.35 mm)
	dimensions	mezzanine
	dimensions	mezzanine	Depth	6.299 inches (160.00 mm)
	Double-high	module only	Depth	6.299 inches (160.00 mm)

			Thickness	0.662 inches (16.77 mm)
	VMEboard		Thickness	0.662 inches (16.77 mm)

		PC board with	Height	10.309 inches (261.85 mm)
		connectors and
		connectors and	Depth	7.4 inches (188 mm)
		front panel	Depth	7.4 inches (188 mm)
		front panel
			Thickness	0.80 inches (20.32 mm)

Conformance to Requirements

These boards are designed to conform to the requirements of the following specifications:

❏VMEbus Specification (IEEE 1014-87)

❏EIA-232-D Serial Interface Specification, EIA

❏SCSI Specification

2-6

Image 30

Motorola manual Conformance to Requirements, MVME187 General Speciﬁcations, Characteristics SpeciÞcations

Contents

Risc Single Board Computer Installation Guide MVME187 Restricted Rights Legend Assembly Item Board Description Preface Safety Summary Safety Depends On You Copyright Motorola All Rights Reserved March Page Contents Page Page Page Page Page List of Figures List of Tables This Chapter Covers About this Manual Signal Name Conventions Data and Address Parameter Numeric Formats Assertion and Negation Conventions Data and Address Size DeﬁnitionsBig-Endian Byte Ordering Control and Status Bit Deﬁnitions True/False Bit State DeﬁnitionsBit Value Descriptions Related Documentation Document Set for MVME187-0xxBoardMotorola Description Publication Number Single Board Computers Scsi Software UserÕs Manual Additional Manuals for this BoardOther Applicable Motorola Publications Motorola Description Non-Motorola Peripheral Controllers Publications Bundle Part Number Description SBCCOMPS/L Applicable Non-Motorola Publications Document Title Source Introduction to the MVME187 Installation Guide Board Level Hardware Description General Description Onboard Memory Mezzanine Module Scsi Mass Storage Interface Parallel Printer Port Serial Function Synchronous Signals Bit RatesSerial Ports Ethernet Transceiver Interface Features 187Bug Firmware Features Conformance to Requirements Characteristics SpeciÞcationsSpeciﬁcations MVME187 General Speciﬁcations Connectors Board Level OverviewAdapters Transition Modules ASICs PCCchip2 Asic VMEchip2 AsicBus Transfers Transfer type Can be Functional Description MEMC040 Memory Controller AsicMcecc Memory Controller Asic Switch Description Front Panel Switches and LEDsFront Panel Switches Front Panel LEDs Data Bus Structure M88000 MPULocal Bus Arbitration Programmable Eprom Features Static RAM Optional Sram Battery Backup See Optional Sram Backup Power Source Select Header J6 on Onboard Dram Stacking Mezzanines Dram Programming Considerations Battery Backed Up RAM and Clock VMEbus Interface InterfacesSerial Port Interface Serial Interface Programming Considerations Status Pins Control PinsParallel Port Interface Ethernet Interface Buffer Overruns Scsi Interface Local Bus Timeout Programmable Tick TimersWatchdog Timer Local Resources Memory Maps Local Bus Memory MapNormal Address Range Devices Range Address Software Devices Accessed Port SizeLocal Bus Memory Map Inhibit Address Range Devices Accessed Port Size Local I/O Devices Memory Map $FFFE000B Iack Level VMEbus Accesses to the Local Bus VMEbus Memory MapVMEbus Short I/O Memory Map Hardware Preparation and Installation Unpacking the Equipment Startup Overview Overview of Startup ProcedureInstall your MVME187 in the chassis Stage What you will need to do Refer to Prepare the MVME187 Complete the installation Stage What you will need to do Refer toConnect peripherals Package for Motorola 88K Modifying Conﬁguration before Installation Preparing the HardwareOption Modiﬁcation MVME187 Switches, Headers, Connectors, Fuses, and LEDs Eprom Location Jumper SettingsChecking the 187Bug EPROMs Eprom Orientation Optional Jumper Settings General Purpose Software Readable Header J1 J1 Bit Descriptions Factory Settings for J1 General Purpose Readable JumpersBit J1 Pins Description Header ConÞguration Jumpers Number Description Settings for J2 System Controller Header System Controller Header J2 Optional Sram Backup Power Source Select Header J6 Serial Port 4 Clock Conﬁguration Select Headers J7 and J8 Primary source VMEbus Number Description Preparing the MVME187 for Installation MVME187 Preparation ProcedureAction Chassis Preparation/Slot Selection Procedure Preparing the System ChassisStep Action Installing the Hardware Installing the MVME187 in the ChassisMVME187 Installation Procedure Transition Modules and Adapter Boards Overview Typical Internal Scsi and Serial Port Connections Equipment Connections 10. Peripheral ConnectionsEquipment Type Connect Through Installing Transition Modules and Adapter Boards Connecting Peripherals 12. Peripheral Connection Procedures Action Refer to Using MVME712A/AM and MVME712B Typical Transition Module Peripheral Port Connectors Starting the System Completing the Installation13. Installation Completion Procedure 14. System Startup Overview System Mode Powering Up the SystemIf 187Bug is Board Mode Initializing the Real-Time Clock 15. RTC Initialization Procedure Step Action Board Mode System ModeProgramming the PCCchip2 and VMEchip2 System Considerations Backplane Power ConnectionsGlobal Bus Timeout Memory Address Ranges Multiple Module Cage Conﬁguration Gcsr Location Monitor RegisterEthernet LAN +12 Vdc Fuse Scsi Bus Termination Storage and the Real-Time Clock Hardware Preparation and Installation Introduction to MVME187Bug Overview of M88000 Firmware Command Facilities Description of 187BugTrap #496 Routines Debugger or Diagnostic Directories Keyboard Control Comparison with M68000-Based Firmware 187Bug Implementation Booting and Restarting 187Bug Memory Requirements Autoboot Autoboot SequenceStarting Up 187Bug ROMboot ROMboot Sequence Network Boot Network Boot SequenceRequirement Optionally, with the ENV command Restarting the System Reset Abort Abort Sequence Break SYSFAIL* Assertion/Negation MPU Clock Speed Calculation Parameter Tables Disk I/O SupportDisk Support Facilities Supported Controllers Blocks Versus Sectors Device Probe Function Disk I/O via 187Bug Commands BH Bootstrap and Halt Controller Command PacketsDisk I/O via 187Bug System Calls Default 187Bug Controller and Device Parameters These commands Status is Command Disk I/O Error CodesUsing When you invoke one Change BO or BH Network I/O Support Intel 82596 LAN Coprocessor Ethernet DriverUDP/IP Protocol Modules RARP/ARP Protocol Modules Bootp Protocol ModuleNetwork Boot Control Module Tftp Protocol Module Network I/O Error Codes Multiprocessor SupportMultiprocessor Control Register Mpcr Method Mpcr Powerup Sequence Mpcr Status CodesMultiprocessor Address Register Mpar Multiprocessor Support Global Control and Status Register Gcsr Method Diagnostic Facilities Diagnostic Monitor Commands/PreﬁxesCommand Description PreÞx Diagnostic Utilities Command Description Write loop enable Read loop enable 187Bug Diagnostic Test Groups Diagnostic Test Groups Debugger General Information Entering Debugger Command Lines Terminal Input/Output Control More characters to it. You can edit the line by Debugger Command Syntax Syntactic Variables Expression as a ParameterBase IdentiÞer Examples Address as a Parameter String Numeric Value LiteralExpression Result In Hex Address Formats Port Numbers Offset Registers Entering and Debugging Programs Creating a Program with the Assembler/DisassemblerDownloading an S-Record Object File Calling System Utilities from User Programs Read the Program from Disk Preserving the Debugger Operating Environment 187Bug Vector Table and Workspace Exception Vectors Used by 187Bug Floating Point SupportHardware Functions CPU/MPU Registers Integer Data Types Floating Point Data Types Single Precision Real Double Precision Real Scientiﬁc Notation 187Bug Debugger Command Set Debugger Commands ENV D Cnfg I MCS range B H W IOI C L Nopa port Niot HAZn a Nopf port Time C L O RL addr B H WSYM addr VER E This Appendix Covers Conﬁguring the Board Information BlockCnfg IM Configure and Environment Commands Setting Environment to Bug/Operating System Table A-1. ENV Command Parameters ENV Parameter and Options Default Meaning of Default First location tested when the Bug LUN Network Auto Boot ConÞguration Memory Search Ending Address Slave address decoders setup Guide Base address of the VMEbus resource This will be the local bus address Table A-1. ENV Command Parameters Configure and Environment Commands Disk/Tape Controller Modules Supported Controller Type First SecondAddress Disk/Tape Controller Default Conﬁgurations $XXXXXXXX MVME327A -- 9 Devices Controller LUN Address Device LUN Device Type IOT Command Parameters for Supported Floppy Types IOT Parameter Floppy Types and Formats Other Characteristics Disk/Tape Controller Data Network Controller Modules Supported Table C-1. Network Controller Access DataDebugger Commands Debugger System Calls Address Interface $FFFFA400 Table D-1. Troubleshooting Steps Condition Possible Try This Problem Troubleshooting the MVME187 Solving Startup Problems Table D-1. Troubleshooting Steps Set mmddyyhhmm Return Envd ReturnReturn Env Return St ReturnDe Return Troubleshooting the MVME187 Solving Startup Problems EEIA-232-D Interconnections Introduction Pin Signal Name and DescriptionTable E-1. EIA-232-D Interconnections Number Mnemonic Signal Name and Description Number Mnemonic Levels of Implementation Signal Adaptations Sample Conﬁgurations Figure E-1. Middle-of-the-Road EIA-232-D Conﬁguration Figure E-2. Minimum EIA-232-D Connection Proper Grounding EIA-232-D Interconnections Index Bootp Default configurations B-2 IN-12 Local bus Local I/O devices 2-26VMEbus 2-28VMEbus short I/O IN-14 See also CD2401 scientific notation 5-14 Scon LED Nvram XON/XOFF