Battery Backed Up RAM and Clock | Motorola MVME187 instruction

Functional Description

Battery Backed Up RAM and Clock

The MK48T08 RAM and clock chip is a 28-pin package that provides

❏A time-of-day clock

❏An oscillator

❏A crystal

❏Power fail detection

❏Memory write protection

❏8KB of RAM

❏A battery

The clock provides

❏Seconds, minutes, hours, day, date, month, and year in BCD 24-hour format

❏Automatic corrections for 28-, 29- (leap year), and 30-day months

No interrupts are generated by the clock.

The MK48T08 is an 8 bit device; however, the interface provided by the PCCchip2 supports 8-, 16-, and 32-bit accesses to the MK48T08.

Refer to the MK48T08 data sheet for detailed programming information.

2

2-17

Image 41

Motorola MVME187 manual Battery Backed Up RAM and Clock

Contents

MVME187 Risc Single Board Computer Installation Guide Restricted Rights Legend Preface Assembly Item Board Description Safety Summary Safety Depends On You Copyright Motorola All Rights Reserved March Page Contents Page Page Page Page Page List of Figures List of Tables About this Manual This Chapter Covers Data and Address Parameter Numeric Formats Signal Name Conventions Big-Endian Byte Ordering Assertion and Negation ConventionsData and Address Size Deﬁnitions Bit Value Descriptions Control and Status Bit DeﬁnitionsTrue/False Bit State Deﬁnitions Motorola Description Publication Number Related DocumentationDocument Set for MVME187-0xxBoard Other Applicable Motorola Publications Additional Manuals for this BoardSingle Board Computers Scsi Software UserÕs Manual Motorola Description Part Number Description Non-Motorola Peripheral Controllers Publications Bundle SBCCOMPS/L Document Title Source Applicable Non-Motorola Publications Introduction to the MVME187 Installation Guide General Description Board Level Hardware Description Scsi Mass Storage Interface Onboard Memory Mezzanine Module Serial Ports Serial Function Synchronous Signals Bit RatesParallel Printer Port Ethernet Transceiver Interface 187Bug Firmware Features Features Speciﬁcations Characteristics SpeciÞcationsConformance to Requirements MVME187 General Speciﬁcations Adapters ConnectorsBoard Level Overview ASICs Transition Modules Bus Transfers VMEchip2 AsicPCCchip2 Asic Transfer type Can be Mcecc Memory Controller Asic Functional DescriptionMEMC040 Memory Controller Asic Front Panel Switches Front Panel Switches and LEDsSwitch Description Front Panel LEDs Local Bus Arbitration Data Bus StructureM88000 MPU Static RAM Programmable Eprom Features See Optional Sram Backup Power Source Select Header J6 on Optional Sram Battery Backup Onboard Dram Dram Programming Considerations Stacking Mezzanines Battery Backed Up RAM and Clock Serial Port Interface VMEbus InterfaceInterfaces Serial Interface Programming Considerations Parallel Port Interface Status PinsControl Pins Ethernet Interface Scsi Interface Buffer Overruns Watchdog Timer Programmable Tick TimersLocal Bus Timeout Local Resources Normal Address Range Devices Memory MapsLocal Bus Memory Map Local Bus Memory Map Address Software Devices Accessed Port SizeRange Inhibit Local I/O Devices Memory Map Address Range Devices Accessed Port Size $FFFE000B Iack Level VMEbus Short I/O Memory Map VMEbus Accesses to the Local BusVMEbus Memory Map Unpacking the Equipment Hardware Preparation and Installation Install your MVME187 in the chassis Overview of Startup ProcedureStartup Overview Stage What you will need to do Refer to Prepare the MVME187 Connect peripherals Complete the installationStage What you will need to do Refer to Package for Motorola 88K Option Modiﬁcation Modifying Conﬁguration before InstallationPreparing the Hardware MVME187 Switches, Headers, Connectors, Fuses, and LEDs Checking the 187Bug EPROMs Jumper SettingsEprom Location Eprom Orientation General Purpose Software Readable Header J1 Optional Jumper Settings Bit J1 Pins Description Factory Settings for J1 General Purpose Readable JumpersJ1 Bit Descriptions Header ConÞguration Jumpers Number Description System Controller Header J2 Settings for J2 System Controller Header Serial Port 4 Clock Conﬁguration Select Headers J7 and J8 Optional Sram Backup Power Source Select Header J6 Primary source VMEbus Number Description Action Preparing the MVME187 for InstallationMVME187 Preparation Procedure Step Action Chassis Preparation/Slot Selection ProcedurePreparing the System Chassis MVME187 Installation Procedure Installing the HardwareInstalling the MVME187 in the Chassis Transition Modules and Adapter Boards Overview Typical Internal Scsi and Serial Port Connections Equipment Type Connect Through Equipment Connections10. Peripheral Connections Connecting Peripherals Installing Transition Modules and Adapter Boards Action Refer to 12. Peripheral Connection Procedures Using MVME712A/AM and MVME712B Typical Transition Module Peripheral Port Connectors 13. Installation Completion Procedure Completing the InstallationStarting the System 14. System Startup Overview If 187Bug is Board Mode Powering Up the SystemSystem Mode Initializing the Real-Time Clock Programming the PCCchip2 and VMEchip2 15. RTC Initialization ProcedureStep Action Board Mode System Mode Global Bus Timeout Backplane Power ConnectionsSystem Considerations Memory Address Ranges Ethernet LAN +12 Vdc Fuse Multiple Module Cage ConﬁgurationGcsr Location Monitor Register Storage and the Real-Time Clock Scsi Bus Termination Hardware Preparation and Installation Overview of M88000 Firmware Introduction to MVME187Bug Trap #496 Routines Command FacilitiesDescription of 187Bug Keyboard Control Debugger or Diagnostic Directories 187Bug Implementation Comparison with M68000-Based Firmware Memory Requirements Booting and Restarting 187Bug Starting Up 187Bug AutobootAutoboot Sequence ROMboot Sequence ROMboot Requirement Optionally, with the ENV command Network BootNetwork Boot Sequence Restarting the System Abort Reset Break Abort Sequence MPU Clock Speed Calculation SYSFAIL* Assertion/Negation Disk Support Facilities Disk I/O SupportParameter Tables Supported Controllers Device Probe Function Blocks Versus Sectors Disk I/O via 187Bug Commands Disk I/O via 187Bug System Calls BH Bootstrap and HaltController Command Packets Default 187Bug Controller and Device Parameters Using When you invoke one Change Disk I/O Error CodesThese commands Status is Command BO or BH UDP/IP Protocol Modules Network I/O SupportIntel 82596 LAN Coprocessor Ethernet Driver Network Boot Control Module Bootp Protocol ModuleRARP/ARP Protocol Modules Tftp Protocol Module Multiprocessor Control Register Mpcr Method Network I/O Error CodesMultiprocessor Support Multiprocessor Address Register Mpar Mpcr Powerup SequenceMpcr Status Codes Multiprocessor Support Global Control and Status Register Gcsr Method Command Description PreÞx Diagnostic FacilitiesDiagnostic Monitor Commands/Preﬁxes Command Description Write loop enable Read loop enable Diagnostic Utilities Diagnostic Test Groups 187Bug Diagnostic Test Groups Debugger General Information Terminal Input/Output Control Entering Debugger Command Lines More characters to it. You can edit the line by Debugger Command Syntax Base IdentiÞer Examples Syntactic VariablesExpression as a Parameter Expression Result In Hex Address as a ParameterString Numeric Value Literal Address Formats Offset Registers Port Numbers Downloading an S-Record Object File Entering and Debugging ProgramsCreating a Program with the Assembler/Disassembler Read the Program from Disk Calling System Utilities from User Programs 187Bug Vector Table and Workspace Preserving the Debugger Operating Environment Hardware Functions Floating Point SupportException Vectors Used by 187Bug CPU/MPU Registers Floating Point Data Types Integer Data Types Double Precision Real Single Precision Real Scientiﬁc Notation Debugger Commands 187Bug Debugger Command Set CS range B H W Cnfg I MENV D IOI C L Zn a Niot HANopa port Nopf port SYM addr RL addr B H WTime C L O VER E Cnfg IM This Appendix CoversConﬁguring the Board Information Block Configure and Environment Commands Setting Environment to Bug/Operating System ENV Parameter and Options Default Meaning of Default Table A-1. ENV Command Parameters First location tested when the Bug LUN Network Auto Boot ConÞguration Memory Search Ending Address Slave address decoders setup Guide Base address of the VMEbus resource This will be the local bus address Table A-1. ENV Command Parameters Configure and Environment Commands Address Disk/Tape Controller Modules SupportedController Type First Second $XXXXXXXX Disk/Tape Controller Default Conﬁgurations Controller LUN Address Device LUN Device Type MVME327A -- 9 Devices IOT Parameter Floppy Types and Formats IOT Command Parameters for Supported Floppy Types Other Characteristics Disk/Tape Controller Data Debugger Commands Debugger System Calls Table C-1. Network Controller Access DataNetwork Controller Modules Supported Address Interface $FFFFA400 Condition Possible Try This Problem Table D-1. Troubleshooting Steps Troubleshooting the MVME187 Solving Startup Problems Table D-1. Troubleshooting Steps Return Set mmddyyhhmm ReturnEnvd Return De Return Env ReturnSt Return Troubleshooting the MVME187 Solving Startup Problems Introduction EEIA-232-D Interconnections Table E-1. EIA-232-D Interconnections Signal Name and DescriptionPin Number Mnemonic Levels of Implementation Signal Name and Description Number Mnemonic Sample Conﬁgurations Signal Adaptations Figure E-1. Middle-of-the-Road EIA-232-D Conﬁguration Figure E-2. Minimum EIA-232-D Connection Proper Grounding EIA-232-D Interconnections Index Bootp Default configurations B-2 IN-12 Local bus Local I/O devices 2-26VMEbus 2-28VMEbus short I/O IN-14 See also CD2401 scientific notation 5-14 Scon LED Nvram XON/XOFF