Applicable Non-Motorola Publications | Motorola MVME187 specs

Related Documentation

Applicable Non-Motorola Publications

The following non-Motorola publications are also available from the sources indicated.

	Document Title	Source

	Versatile Backplane Bus: VMEbus,	The Institute of Electrical and
	ANSI/IEEE Std 1014-1987	Electronics Engineers, Inc.
	(VMEbus SpeciÞcation) (This is also	345 East 47th St.
	Microprocessor System Bus for 1 to 4 Byte	New York, NY 10017
	Data, IEC 821 BUS)
	Data, IEC 821 BUS)	Bureau Central de la Commission
		Bureau Central de la Commission
		Electrotechnique Internationale
		3, rue de VarembŽ
		Geneva, Switzerland

	ANSI Small Computer System Interface-2	Global Engineering Documents
	(SCSI-2), Draft Document X3.131-198X,	15 Inverness Way East
	Revision 10c	Englewood, CO 80112-5704

	CL-CD2400/2401 Four-Channel Multi-	Cirrus Logic, Inc.
	Protocol Communications Controller Data	3100 West Warren Ave.
	Sheet, order number 542400-003	Fremont, CA 94538

	82596CA Local Area Network Coprocessor	Intel Corporation, Literature Sales
	Data Sheet, order number 290218; and	P.O. Box 58130
	82596 User's Manual, order number 296853	Santa Clara, CA 95052-8130

	NCR 53C710 SCSI I/O Processor Data	NCR Corporation
	Manual, order number NCR53C710DM	Microelectronics Products Division
		1635 Aeroplaza Dr.
	NCR 53C710 SCSI I/O Processor	1635 Aeroplaza Dr.
	NCR 53C710 SCSI I/O Processor	Colorado Springs, CO 80916
	ProgrammerÕs Guide, order number	Colorado Springs, CO 80916
	ProgrammerÕs Guide, order number
	NCR53C710PG

	MK48T08(B) Timekeeper TM and 8Kx8	SGS-THOMSON Microelectronics
	Zeropower TM RAM data sheet in Static	Group
	RAMs Databook, order number DBSRAM71	Marketing Headquarters
		1000 East Bell Rd.
		Phoenix, AZ 85022-2699

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Motorola MVME187 manual Applicable Non-Motorola Publications, Document Title Source

Contents

MVME187 Risc Single Board Computer Installation Guide Restricted Rights Legend Preface Assembly Item Board Description Safety Summary Safety Depends On You Copyright Motorola All Rights Reserved March Page Contents Page Page Page Page Page List of Figures List of Tables About this Manual This Chapter Covers Data and Address Parameter Numeric Formats Signal Name Conventions Big-Endian Byte Ordering Assertion and Negation ConventionsData and Address Size Deﬁnitions Bit Value Descriptions Control and Status Bit DeﬁnitionsTrue/False Bit State Deﬁnitions Motorola Description Publication Number Related DocumentationDocument Set for MVME187-0xxBoard Motorola Description Additional Manuals for this BoardOther Applicable Motorola Publications Single Board Computers Scsi Software UserÕs Manual Part Number Description Non-Motorola Peripheral Controllers Publications Bundle SBCCOMPS/L Document Title Source Applicable Non-Motorola Publications Introduction to the MVME187 Installation Guide General Description Board Level Hardware Description Scsi Mass Storage Interface Onboard Memory Mezzanine Module Ethernet Transceiver Interface Serial Function Synchronous Signals Bit RatesSerial Ports Parallel Printer Port 187Bug Firmware Features Features MVME187 General Speciﬁcations Characteristics SpeciÞcationsSpeciﬁcations Conformance to Requirements Adapters ConnectorsBoard Level Overview ASICs Transition Modules Transfer type Can be VMEchip2 AsicBus Transfers PCCchip2 Asic Mcecc Memory Controller Asic Functional DescriptionMEMC040 Memory Controller Asic Front Panel LEDs Front Panel Switches and LEDsFront Panel Switches Switch Description Local Bus Arbitration Data Bus StructureM88000 MPU Static RAM Programmable Eprom Features See Optional Sram Backup Power Source Select Header J6 on Optional Sram Battery Backup Onboard Dram Dram Programming Considerations Stacking Mezzanines Battery Backed Up RAM and Clock Serial Port Interface VMEbus InterfaceInterfaces Serial Interface Programming Considerations Parallel Port Interface Status PinsControl Pins Ethernet Interface Scsi Interface Buffer Overruns Local Resources Programmable Tick TimersWatchdog Timer Local Bus Timeout Normal Address Range Devices Memory MapsLocal Bus Memory Map Inhibit Address Software Devices Accessed Port SizeLocal Bus Memory Map Range Local I/O Devices Memory Map Address Range Devices Accessed Port Size $FFFE000B Iack Level VMEbus Short I/O Memory Map VMEbus Accesses to the Local BusVMEbus Memory Map Unpacking the Equipment Hardware Preparation and Installation Stage What you will need to do Refer to Prepare the MVME187 Overview of Startup ProcedureInstall your MVME187 in the chassis Startup Overview Connect peripherals Complete the installationStage What you will need to do Refer to Package for Motorola 88K Option Modiﬁcation Modifying Conﬁguration before InstallationPreparing the Hardware MVME187 Switches, Headers, Connectors, Fuses, and LEDs Eprom Orientation Jumper SettingsChecking the 187Bug EPROMs Eprom Location General Purpose Software Readable Header J1 Optional Jumper Settings Header ConÞguration Jumpers Number Description Factory Settings for J1 General Purpose Readable JumpersBit J1 Pins Description J1 Bit Descriptions System Controller Header J2 Settings for J2 System Controller Header Serial Port 4 Clock Conﬁguration Select Headers J7 and J8 Optional Sram Backup Power Source Select Header J6 Primary source VMEbus Number Description Action Preparing the MVME187 for InstallationMVME187 Preparation Procedure Step Action Chassis Preparation/Slot Selection ProcedurePreparing the System Chassis MVME187 Installation Procedure Installing the HardwareInstalling the MVME187 in the Chassis Transition Modules and Adapter Boards Overview Typical Internal Scsi and Serial Port Connections Equipment Type Connect Through Equipment Connections10. Peripheral Connections Connecting Peripherals Installing Transition Modules and Adapter Boards Action Refer to 12. Peripheral Connection Procedures Using MVME712A/AM and MVME712B Typical Transition Module Peripheral Port Connectors 14. System Startup Overview Completing the Installation13. Installation Completion Procedure Starting the System Initializing the Real-Time Clock Powering Up the SystemIf 187Bug is Board Mode System Mode Programming the PCCchip2 and VMEchip2 15. RTC Initialization ProcedureStep Action Board Mode System Mode Memory Address Ranges Backplane Power ConnectionsGlobal Bus Timeout System Considerations Ethernet LAN +12 Vdc Fuse Multiple Module Cage ConﬁgurationGcsr Location Monitor Register Storage and the Real-Time Clock Scsi Bus Termination Hardware Preparation and Installation Overview of M88000 Firmware Introduction to MVME187Bug Trap #496 Routines Command FacilitiesDescription of 187Bug Keyboard Control Debugger or Diagnostic Directories 187Bug Implementation Comparison with M68000-Based Firmware Memory Requirements Booting and Restarting 187Bug Starting Up 187Bug AutobootAutoboot Sequence ROMboot Sequence ROMboot Requirement Optionally, with the ENV command Network BootNetwork Boot Sequence Restarting the System Abort Reset Break Abort Sequence MPU Clock Speed Calculation SYSFAIL* Assertion/Negation Supported Controllers Disk I/O SupportDisk Support Facilities Parameter Tables Device Probe Function Blocks Versus Sectors Disk I/O via 187Bug Commands Disk I/O via 187Bug System Calls BH Bootstrap and HaltController Command Packets Default 187Bug Controller and Device Parameters BO or BH Disk I/O Error CodesUsing When you invoke one Change These commands Status is Command UDP/IP Protocol Modules Network I/O SupportIntel 82596 LAN Coprocessor Ethernet Driver Tftp Protocol Module Bootp Protocol ModuleNetwork Boot Control Module RARP/ARP Protocol Modules Multiprocessor Control Register Mpcr Method Network I/O Error CodesMultiprocessor Support Multiprocessor Address Register Mpar Mpcr Powerup SequenceMpcr Status Codes Multiprocessor Support Global Control and Status Register Gcsr Method Command Description PreÞx Diagnostic FacilitiesDiagnostic Monitor Commands/Preﬁxes Command Description Write loop enable Read loop enable Diagnostic Utilities Diagnostic Test Groups 187Bug Diagnostic Test Groups Debugger General Information Terminal Input/Output Control Entering Debugger Command Lines More characters to it. You can edit the line by Debugger Command Syntax Base IdentiÞer Examples Syntactic VariablesExpression as a Parameter Expression Result In Hex Address as a ParameterString Numeric Value Literal Address Formats Offset Registers Port Numbers Downloading an S-Record Object File Entering and Debugging ProgramsCreating a Program with the Assembler/Disassembler Read the Program from Disk Calling System Utilities from User Programs 187Bug Vector Table and Workspace Preserving the Debugger Operating Environment CPU/MPU Registers Floating Point SupportHardware Functions Exception Vectors Used by 187Bug Floating Point Data Types Integer Data Types Double Precision Real Single Precision Real Scientiﬁc Notation Debugger Commands 187Bug Debugger Command Set IOI C L Cnfg I MCS range B H W ENV D Nopf port Niot HAZn a Nopa port VER E RL addr B H WSYM addr Time C L O Cnfg IM This Appendix CoversConﬁguring the Board Information Block Configure and Environment Commands Setting Environment to Bug/Operating System ENV Parameter and Options Default Meaning of Default Table A-1. ENV Command Parameters First location tested when the Bug LUN Network Auto Boot ConÞguration Memory Search Ending Address Slave address decoders setup Guide Base address of the VMEbus resource This will be the local bus address Table A-1. ENV Command Parameters Configure and Environment Commands Address Disk/Tape Controller Modules SupportedController Type First Second $XXXXXXXX Disk/Tape Controller Default Conﬁgurations Controller LUN Address Device LUN Device Type MVME327A -- 9 Devices IOT Parameter Floppy Types and Formats IOT Command Parameters for Supported Floppy Types Other Characteristics Disk/Tape Controller Data Address Interface Table C-1. Network Controller Access DataDebugger Commands Debugger System Calls Network Controller Modules Supported $FFFFA400 Condition Possible Try This Problem Table D-1. Troubleshooting Steps Troubleshooting the MVME187 Solving Startup Problems Table D-1. Troubleshooting Steps Return Set mmddyyhhmm ReturnEnvd Return De Return Env ReturnSt Return Troubleshooting the MVME187 Solving Startup Problems Introduction EEIA-232-D Interconnections Number Mnemonic Signal Name and DescriptionTable E-1. EIA-232-D Interconnections Pin Levels of Implementation Signal Name and Description Number Mnemonic Sample Conﬁgurations Signal Adaptations Figure E-1. Middle-of-the-Road EIA-232-D Conﬁguration Figure E-2. Minimum EIA-232-D Connection Proper Grounding EIA-232-D Interconnections Index Bootp Default configurations B-2 IN-12 Local bus Local I/O devices 2-26VMEbus 2-28VMEbus short I/O IN-14 See also CD2401 scientific notation 5-14 Scon LED Nvram XON/XOFF