J1 Bit Descriptions, Bit J1 Pins Description | Motorola MVME187

			Preparing the Hardware
			Table 3-2. J1 Bit Descriptions

	Bit	J1 Pins	Description

	Bit #0 (GPI0)	1-2	When this bit is a one (high), it instructs the debugger to use
			local Static RAM for its work page (i.e., variables, stack, vector
			tables, etc.). This bit will be high when jumper is removed.

	Bit #1 (GPI1)	3-4	When this bit is a one (high), it instructs the debugger to use
			the default setup/operation parameters in ROM versus the
			user setup/operation parameters in NVRAM. This is the same
			as depressing the RESET and ABORT switches at the same
			time. This feature can be used in the event the user setup is
			corrupted or does not meet a sanity check. Refer to the ENV
			command (Appendix A) for the ROM defaults. This bit will be
			high when jumper is removed.

	Bit #2 (GPI2)	5-6	Reserved for future use.

	Bit #3 (GPI3)	7-8	Reserved for future use.

	Bit #4 (GPI4)	9-10	Open to your application.

	Bit #5 (GPI5)	11-12	Open to your application.

	Bit #6 (GPI6)	13-14	Open to your application.

	Bit #7 (GPI7)	15-16	Open to your application.

Table 3-3. Factory Settings for J1 General Purpose Readable Jumpers

Header

Header

ConÞguration

Jumpers

Number

Description

GPI0 - GPI3:

GPI7

GPI6

GPI5

GPI4

GPI3

GPI2

GPI1

GPI0

General

Reserved

J1

purpose

GPI4 - GPI7:

15

7

1

software

User-deÞnable

readable

jumpers

(Factory

16

8

2

conÞguration)

3

3-9

Image 61

Motorola MVME187 J1 Bit Descriptions, Factory Settings for J1 General Purpose Readable Jumpers, Bit J1 Pins Description

Contents

MVME187 Risc Single Board Computer Installation Guide Restricted Rights Legend Preface Assembly Item Board Description Safety Summary Safety Depends On You Copyright Motorola All Rights Reserved March Page Contents Page Page Page Page Page List of Figures List of Tables About this Manual This Chapter Covers Data and Address Parameter Numeric Formats Signal Name Conventions Data and Address Size Deﬁnitions Assertion and Negation ConventionsBig-Endian Byte Ordering True/False Bit State Deﬁnitions Control and Status Bit DeﬁnitionsBit Value Descriptions Document Set for MVME187-0xxBoard Related DocumentationMotorola Description Publication Number Other Applicable Motorola Publications Additional Manuals for this BoardSingle Board Computers Scsi Software UserÕs Manual Motorola Description Part Number Description Non-Motorola Peripheral Controllers Publications Bundle SBCCOMPS/L Document Title Source Applicable Non-Motorola Publications Introduction to the MVME187 Installation Guide General Description Board Level Hardware Description Scsi Mass Storage Interface Onboard Memory Mezzanine Module Serial Ports Serial Function Synchronous Signals Bit RatesParallel Printer Port Ethernet Transceiver Interface 187Bug Firmware Features Features Speciﬁcations Characteristics SpeciÞcationsConformance to Requirements MVME187 General Speciﬁcations Board Level Overview ConnectorsAdapters ASICs Transition Modules Bus Transfers VMEchip2 AsicPCCchip2 Asic Transfer type Can be MEMC040 Memory Controller Asic Functional DescriptionMcecc Memory Controller Asic Front Panel Switches Front Panel Switches and LEDsSwitch Description Front Panel LEDs M88000 MPU Data Bus StructureLocal Bus Arbitration Static RAM Programmable Eprom Features See Optional Sram Backup Power Source Select Header J6 on Optional Sram Battery Backup Onboard Dram Dram Programming Considerations Stacking Mezzanines Battery Backed Up RAM and Clock Interfaces VMEbus InterfaceSerial Port Interface Serial Interface Programming Considerations Control Pins Status PinsParallel Port Interface Ethernet Interface Scsi Interface Buffer Overruns Watchdog Timer Programmable Tick TimersLocal Bus Timeout Local Resources Local Bus Memory Map Memory MapsNormal Address Range Devices Local Bus Memory Map Address Software Devices Accessed Port SizeRange Inhibit Local I/O Devices Memory Map Address Range Devices Accessed Port Size $FFFE000B Iack Level VMEbus Memory Map VMEbus Accesses to the Local BusVMEbus Short I/O Memory Map Unpacking the Equipment Hardware Preparation and Installation Install your MVME187 in the chassis Overview of Startup ProcedureStartup Overview Stage What you will need to do Refer to Prepare the MVME187 Stage What you will need to do Refer to Complete the installationConnect peripherals Package for Motorola 88K Preparing the Hardware Modifying Conﬁguration before InstallationOption Modiﬁcation MVME187 Switches, Headers, Connectors, Fuses, and LEDs Checking the 187Bug EPROMs Jumper SettingsEprom Location Eprom Orientation General Purpose Software Readable Header J1 Optional Jumper Settings Bit J1 Pins Description Factory Settings for J1 General Purpose Readable JumpersJ1 Bit Descriptions Header ConÞguration Jumpers Number Description System Controller Header J2 Settings for J2 System Controller Header Serial Port 4 Clock Conﬁguration Select Headers J7 and J8 Optional Sram Backup Power Source Select Header J6 Primary source VMEbus Number Description MVME187 Preparation Procedure Preparing the MVME187 for InstallationAction Preparing the System Chassis Chassis Preparation/Slot Selection ProcedureStep Action Installing the MVME187 in the Chassis Installing the HardwareMVME187 Installation Procedure Transition Modules and Adapter Boards Overview Typical Internal Scsi and Serial Port Connections 10. Peripheral Connections Equipment ConnectionsEquipment Type Connect Through Connecting Peripherals Installing Transition Modules and Adapter Boards Action Refer to 12. Peripheral Connection Procedures Using MVME712A/AM and MVME712B Typical Transition Module Peripheral Port Connectors 13. Installation Completion Procedure Completing the InstallationStarting the System 14. System Startup Overview If 187Bug is Board Mode Powering Up the SystemSystem Mode Initializing the Real-Time Clock Step Action Board Mode System Mode 15. RTC Initialization ProcedureProgramming the PCCchip2 and VMEchip2 Global Bus Timeout Backplane Power ConnectionsSystem Considerations Memory Address Ranges Gcsr Location Monitor Register Multiple Module Cage ConﬁgurationEthernet LAN +12 Vdc Fuse Storage and the Real-Time Clock Scsi Bus Termination Hardware Preparation and Installation Overview of M88000 Firmware Introduction to MVME187Bug Description of 187Bug Command FacilitiesTrap #496 Routines Keyboard Control Debugger or Diagnostic Directories 187Bug Implementation Comparison with M68000-Based Firmware Memory Requirements Booting and Restarting 187Bug Autoboot Sequence AutobootStarting Up 187Bug ROMboot Sequence ROMboot Network Boot Sequence Network BootRequirement Optionally, with the ENV command Restarting the System Abort Reset Break Abort Sequence MPU Clock Speed Calculation SYSFAIL* Assertion/Negation Disk Support Facilities Disk I/O SupportParameter Tables Supported Controllers Device Probe Function Blocks Versus Sectors Disk I/O via 187Bug Commands Controller Command Packets BH Bootstrap and HaltDisk I/O via 187Bug System Calls Default 187Bug Controller and Device Parameters Using When you invoke one Change Disk I/O Error CodesThese commands Status is Command BO or BH Intel 82596 LAN Coprocessor Ethernet Driver Network I/O SupportUDP/IP Protocol Modules Network Boot Control Module Bootp Protocol ModuleRARP/ARP Protocol Modules Tftp Protocol Module Multiprocessor Support Network I/O Error CodesMultiprocessor Control Register Mpcr Method Mpcr Status Codes Mpcr Powerup SequenceMultiprocessor Address Register Mpar Multiprocessor Support Global Control and Status Register Gcsr Method Diagnostic Monitor Commands/Preﬁxes Diagnostic FacilitiesCommand Description PreÞx Command Description Write loop enable Read loop enable Diagnostic Utilities Diagnostic Test Groups 187Bug Diagnostic Test Groups Debugger General Information Terminal Input/Output Control Entering Debugger Command Lines More characters to it. You can edit the line by Debugger Command Syntax Expression as a Parameter Syntactic VariablesBase IdentiÞer Examples String Numeric Value Literal Address as a ParameterExpression Result In Hex Address Formats Offset Registers Port Numbers Creating a Program with the Assembler/Disassembler Entering and Debugging ProgramsDownloading an S-Record Object File Read the Program from Disk Calling System Utilities from User Programs 187Bug Vector Table and Workspace Preserving the Debugger Operating Environment Hardware Functions Floating Point SupportException Vectors Used by 187Bug CPU/MPU Registers Floating Point Data Types Integer Data Types Double Precision Real Single Precision Real Scientiﬁc Notation Debugger Commands 187Bug Debugger Command Set CS range B H W Cnfg I MENV D IOI C L Zn a Niot HANopa port Nopf port SYM addr RL addr B H WTime C L O VER E Conﬁguring the Board Information Block This Appendix CoversCnfg IM Configure and Environment Commands Setting Environment to Bug/Operating System ENV Parameter and Options Default Meaning of Default Table A-1. ENV Command Parameters First location tested when the Bug LUN Network Auto Boot ConÞguration Memory Search Ending Address Slave address decoders setup Guide Base address of the VMEbus resource This will be the local bus address Table A-1. ENV Command Parameters Configure and Environment Commands Controller Type First Second Disk/Tape Controller Modules SupportedAddress $XXXXXXXX Disk/Tape Controller Default Conﬁgurations Controller LUN Address Device LUN Device Type MVME327A -- 9 Devices IOT Parameter Floppy Types and Formats IOT Command Parameters for Supported Floppy Types Other Characteristics Disk/Tape Controller Data Debugger Commands Debugger System Calls Table C-1. Network Controller Access DataNetwork Controller Modules Supported Address Interface $FFFFA400 Condition Possible Try This Problem Table D-1. Troubleshooting Steps Troubleshooting the MVME187 Solving Startup Problems Table D-1. Troubleshooting Steps Envd Return Set mmddyyhhmm ReturnReturn St Return Env ReturnDe Return Troubleshooting the MVME187 Solving Startup Problems Introduction EEIA-232-D Interconnections Table E-1. EIA-232-D Interconnections Signal Name and DescriptionPin Number Mnemonic Levels of Implementation Signal Name and Description Number Mnemonic Sample Conﬁgurations Signal Adaptations Figure E-1. Middle-of-the-Road EIA-232-D Conﬁguration Figure E-2. Minimum EIA-232-D Connection Proper Grounding EIA-232-D Interconnections Index Bootp Default configurations B-2 IN-12 Local bus Local I/O devices 2-26VMEbus 2-28VMEbus short I/O IN-14 See also CD2401 scientific notation 5-14 Scon LED Nvram XON/XOFF