Buffer Overruns, Scsi Interface | Motorola MVME187 instruction

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Board Level Hardware Description

Buffer Overruns

Because the 82596CA has small internal buffers and the VMEbus has an undefined latency period, buffer overrun may occur if the DMA is programmed to access the VMEbus. Therefore, the 82596CA should not be programmed to access the VMEbus. Support functions for the 82596CA are provided by the PCCchip2.

Refer to the 82596CA user's guide for detailed programming information.

SCSI Interface

The MVME187 provides for mass storage subsystems through the industry-standard SCSI bus. These subsystems may include hard and floppy disk drives, streaming tape drives, and other mass storage devices.

The SCSI interface is implemented using the NCR 53C710 SCSI I/O controller.

Support functions for the 53C710 are provided by the PCCchip2. Refer to the 53C710 user's guide for detailed programming information.

SCSI Termination

Because this board has no provision for SCSI termination, you must ensure that the SCSI bus is terminated properly.

❏If the SCSI bus ends at the P2 Adapter, termination resistors must be installed on the R1, R2, and R3 sockets using three 8- pin SIP resistors. Note: +5V power to the SCSI bus TERM power line and termination resistors is provided through a fuse located on the P2 transition board.

❏If there are additional SCSI mass storage devices in your system, make sure that terminators are installed on the last device in the SCSI chain.

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Motorola MVME187 manual Buffer Overruns, Scsi Interface

Contents

Risc Single Board Computer Installation Guide MVME187 Restricted Rights Legend Assembly Item Board Description Preface Safety Summary Safety Depends On You Copyright Motorola All Rights Reserved March Page Contents Page Page Page Page Page List of Figures List of Tables This Chapter Covers About this Manual Signal Name Conventions Data and Address Parameter Numeric Formats Data and Address Size Deﬁnitions Assertion and Negation ConventionsBig-Endian Byte Ordering True/False Bit State Deﬁnitions Control and Status Bit DeﬁnitionsBit Value Descriptions Document Set for MVME187-0xxBoard Related DocumentationMotorola Description Publication Number Single Board Computers Scsi Software UserÕs Manual Additional Manuals for this BoardOther Applicable Motorola Publications Motorola Description Non-Motorola Peripheral Controllers Publications Bundle Part Number Description SBCCOMPS/L Applicable Non-Motorola Publications Document Title Source Introduction to the MVME187 Installation Guide Board Level Hardware Description General Description Onboard Memory Mezzanine Module Scsi Mass Storage Interface Parallel Printer Port Serial Function Synchronous Signals Bit RatesSerial Ports Ethernet Transceiver Interface Features 187Bug Firmware Features Conformance to Requirements Characteristics SpeciÞcationsSpeciﬁcations MVME187 General Speciﬁcations Board Level Overview ConnectorsAdapters Transition Modules ASICs PCCchip2 Asic VMEchip2 AsicBus Transfers Transfer type Can be MEMC040 Memory Controller Asic Functional DescriptionMcecc Memory Controller Asic Switch Description Front Panel Switches and LEDsFront Panel Switches Front Panel LEDs M88000 MPU Data Bus StructureLocal Bus Arbitration Programmable Eprom Features Static RAM Optional Sram Battery Backup See Optional Sram Backup Power Source Select Header J6 on Onboard Dram Stacking Mezzanines Dram Programming Considerations Battery Backed Up RAM and Clock Interfaces VMEbus InterfaceSerial Port Interface Serial Interface Programming Considerations Control Pins Status PinsParallel Port Interface Ethernet Interface Buffer Overruns Scsi Interface Local Bus Timeout Programmable Tick TimersWatchdog Timer Local Resources Local Bus Memory Map Memory MapsNormal Address Range Devices Range Address Software Devices Accessed Port SizeLocal Bus Memory Map Inhibit Address Range Devices Accessed Port Size Local I/O Devices Memory Map $FFFE000B Iack Level VMEbus Memory Map VMEbus Accesses to the Local BusVMEbus Short I/O Memory Map Hardware Preparation and Installation Unpacking the Equipment Startup Overview Overview of Startup ProcedureInstall your MVME187 in the chassis Stage What you will need to do Refer to Prepare the MVME187 Stage What you will need to do Refer to Complete the installationConnect peripherals Package for Motorola 88K Preparing the Hardware Modifying Conﬁguration before InstallationOption Modiﬁcation MVME187 Switches, Headers, Connectors, Fuses, and LEDs Eprom Location Jumper SettingsChecking the 187Bug EPROMs Eprom Orientation Optional Jumper Settings General Purpose Software Readable Header J1 J1 Bit Descriptions Factory Settings for J1 General Purpose Readable JumpersBit J1 Pins Description Header ConÞguration Jumpers Number Description Settings for J2 System Controller Header System Controller Header J2 Optional Sram Backup Power Source Select Header J6 Serial Port 4 Clock Conﬁguration Select Headers J7 and J8 Primary source VMEbus Number Description MVME187 Preparation Procedure Preparing the MVME187 for InstallationAction Preparing the System Chassis Chassis Preparation/Slot Selection ProcedureStep Action Installing the MVME187 in the Chassis Installing the HardwareMVME187 Installation Procedure Transition Modules and Adapter Boards Overview Typical Internal Scsi and Serial Port Connections 10. Peripheral Connections Equipment ConnectionsEquipment Type Connect Through Installing Transition Modules and Adapter Boards Connecting Peripherals 12. Peripheral Connection Procedures Action Refer to Using MVME712A/AM and MVME712B Typical Transition Module Peripheral Port Connectors Starting the System Completing the Installation13. Installation Completion Procedure 14. System Startup Overview System Mode Powering Up the SystemIf 187Bug is Board Mode Initializing the Real-Time Clock Step Action Board Mode System Mode 15. RTC Initialization ProcedureProgramming the PCCchip2 and VMEchip2 System Considerations Backplane Power ConnectionsGlobal Bus Timeout Memory Address Ranges Gcsr Location Monitor Register Multiple Module Cage ConﬁgurationEthernet LAN +12 Vdc Fuse Scsi Bus Termination Storage and the Real-Time Clock Hardware Preparation and Installation Introduction to MVME187Bug Overview of M88000 Firmware Description of 187Bug Command FacilitiesTrap #496 Routines Debugger or Diagnostic Directories Keyboard Control Comparison with M68000-Based Firmware 187Bug Implementation Booting and Restarting 187Bug Memory Requirements Autoboot Sequence AutobootStarting Up 187Bug ROMboot ROMboot Sequence Network Boot Sequence Network BootRequirement Optionally, with the ENV command Restarting the System Reset Abort Abort Sequence Break SYSFAIL* Assertion/Negation MPU Clock Speed Calculation Parameter Tables Disk I/O SupportDisk Support Facilities Supported Controllers Blocks Versus Sectors Device Probe Function Disk I/O via 187Bug Commands Controller Command Packets BH Bootstrap and HaltDisk I/O via 187Bug System Calls Default 187Bug Controller and Device Parameters These commands Status is Command Disk I/O Error CodesUsing When you invoke one Change BO or BH Intel 82596 LAN Coprocessor Ethernet Driver Network I/O SupportUDP/IP Protocol Modules RARP/ARP Protocol Modules Bootp Protocol ModuleNetwork Boot Control Module Tftp Protocol Module Multiprocessor Support Network I/O Error CodesMultiprocessor Control Register Mpcr Method Mpcr Status Codes Mpcr Powerup SequenceMultiprocessor Address Register Mpar Multiprocessor Support Global Control and Status Register Gcsr Method Diagnostic Monitor Commands/Preﬁxes Diagnostic FacilitiesCommand Description PreÞx Diagnostic Utilities Command Description Write loop enable Read loop enable 187Bug Diagnostic Test Groups Diagnostic Test Groups Debugger General Information Entering Debugger Command Lines Terminal Input/Output Control More characters to it. You can edit the line by Debugger Command Syntax Expression as a Parameter Syntactic VariablesBase IdentiÞer Examples String Numeric Value Literal Address as a ParameterExpression Result In Hex Address Formats Port Numbers Offset Registers Creating a Program with the Assembler/Disassembler Entering and Debugging ProgramsDownloading an S-Record Object File Calling System Utilities from User Programs Read the Program from Disk Preserving the Debugger Operating Environment 187Bug Vector Table and Workspace Exception Vectors Used by 187Bug Floating Point SupportHardware Functions CPU/MPU Registers Integer Data Types Floating Point Data Types Single Precision Real Double Precision Real Scientiﬁc Notation 187Bug Debugger Command Set Debugger Commands ENV D Cnfg I MCS range B H W IOI C L Nopa port Niot HAZn a Nopf port Time C L O RL addr B H WSYM addr VER E Conﬁguring the Board Information Block This Appendix CoversCnfg IM Configure and Environment Commands Setting Environment to Bug/Operating System Table A-1. ENV Command Parameters ENV Parameter and Options Default Meaning of Default First location tested when the Bug LUN Network Auto Boot ConÞguration Memory Search Ending Address Slave address decoders setup Guide Base address of the VMEbus resource This will be the local bus address Table A-1. ENV Command Parameters Configure and Environment Commands Controller Type First Second Disk/Tape Controller Modules SupportedAddress Disk/Tape Controller Default Conﬁgurations $XXXXXXXX MVME327A -- 9 Devices Controller LUN Address Device LUN Device Type IOT Command Parameters for Supported Floppy Types IOT Parameter Floppy Types and Formats Other Characteristics Disk/Tape Controller Data Network Controller Modules Supported Table C-1. Network Controller Access DataDebugger Commands Debugger System Calls Address Interface $FFFFA400 Table D-1. Troubleshooting Steps Condition Possible Try This Problem Troubleshooting the MVME187 Solving Startup Problems Table D-1. Troubleshooting Steps Envd Return Set mmddyyhhmm ReturnReturn St Return Env ReturnDe Return Troubleshooting the MVME187 Solving Startup Problems EEIA-232-D Interconnections Introduction Pin Signal Name and DescriptionTable E-1. EIA-232-D Interconnections Number Mnemonic Signal Name and Description Number Mnemonic Levels of Implementation Signal Adaptations Sample Conﬁgurations Figure E-1. Middle-of-the-Road EIA-232-D Conﬁguration Figure E-2. Minimum EIA-232-D Connection Proper Grounding EIA-232-D Interconnections Index Bootp Default configurations B-2 IN-12 Local bus Local I/O devices 2-26VMEbus 2-28VMEbus short I/O IN-14 See also CD2401 scientific notation 5-14 Scon LED Nvram XON/XOFF