Comparison with M68000-Based Firmware | Motorola MVME187 instruction

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Debugger General Information

Comparison with M68000-Based Firmware

If you have used one or more of Motorola's other debugging packages, you will find the RISC 187Bug very similar, after making due allowances for the architectural differences between the M68000 and M88000 CPU architectures. These differences are primarily reflected as follows:

❏Instruction mnemonics and addressing modes of the assembler/disassembler differ somewhat in 187Bug.

❏187Bug uses registers instead of the stack for the passing of arguments to or from the TRAP #496 handler.

❏The interactive commands in 187Bug are more consistent. For example, delimiters between commands and arguments may now be commas or spaces interchangeably.

187Bug Implementation

MVME187Bug is written largely in the ÒCÓ programming language, providing benefits of portability and maintainability. Where necessary, assembler has been used in the form of separately compiled modules containing only assembler code; no mixed language modules are used.

Physically, 187Bug is contained in two of the four 44-pin PLCC/CLCC EPROMs, providing 512KB (128K words) of storage. Both EPROMs are necessary regardless of how much space is actually occupied by the firmware, because of the 32-bit word- oriented M88000 memory bus architecture.

The executable code is checksummed at every power-on or reset firmware entry, and the result (which includes a pre-calculated checksum contained in the EPROMs), is tested for an expected zero. Thus, users are cautioned against modification of the EPROMs unless re-checksum precautions are taken.

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Motorola MVME187 manual Comparison with M68000-Based Firmware, 187Bug Implementation

Contents

Risc Single Board Computer Installation Guide MVME187 Restricted Rights Legend Assembly Item Board Description Preface Safety Summary Safety Depends On You Copyright Motorola All Rights Reserved March Page Contents Page Page Page Page Page List of Figures List of Tables This Chapter Covers About this Manual Signal Name Conventions Data and Address Parameter Numeric Formats Big-Endian Byte Ordering Assertion and Negation ConventionsData and Address Size Deﬁnitions Bit Value Descriptions Control and Status Bit DeﬁnitionsTrue/False Bit State Deﬁnitions Motorola Description Publication Number Related DocumentationDocument Set for MVME187-0xxBoard Single Board Computers Scsi Software UserÕs Manual Additional Manuals for this BoardOther Applicable Motorola Publications Motorola Description Non-Motorola Peripheral Controllers Publications Bundle Part Number Description SBCCOMPS/L Applicable Non-Motorola Publications Document Title Source Introduction to the MVME187 Installation Guide Board Level Hardware Description General Description Onboard Memory Mezzanine Module Scsi Mass Storage Interface Parallel Printer Port Serial Function Synchronous Signals Bit RatesSerial Ports Ethernet Transceiver Interface Features 187Bug Firmware Features Conformance to Requirements Characteristics SpeciÞcationsSpeciﬁcations MVME187 General Speciﬁcations Adapters ConnectorsBoard Level Overview Transition Modules ASICs PCCchip2 Asic VMEchip2 AsicBus Transfers Transfer type Can be Mcecc Memory Controller Asic Functional DescriptionMEMC040 Memory Controller Asic Switch Description Front Panel Switches and LEDsFront Panel Switches Front Panel LEDs Local Bus Arbitration Data Bus StructureM88000 MPU Programmable Eprom Features Static RAM Optional Sram Battery Backup See Optional Sram Backup Power Source Select Header J6 on Onboard Dram Stacking Mezzanines Dram Programming Considerations Battery Backed Up RAM and Clock Serial Port Interface VMEbus InterfaceInterfaces Serial Interface Programming Considerations Parallel Port Interface Status PinsControl Pins Ethernet Interface Buffer Overruns Scsi Interface Local Bus Timeout Programmable Tick TimersWatchdog Timer Local Resources Normal Address Range Devices Memory MapsLocal Bus Memory Map Range Address Software Devices Accessed Port SizeLocal Bus Memory Map Inhibit Address Range Devices Accessed Port Size Local I/O Devices Memory Map $FFFE000B Iack Level VMEbus Short I/O Memory Map VMEbus Accesses to the Local BusVMEbus Memory Map Hardware Preparation and Installation Unpacking the Equipment Startup Overview Overview of Startup ProcedureInstall your MVME187 in the chassis Stage What you will need to do Refer to Prepare the MVME187 Connect peripherals Complete the installationStage What you will need to do Refer to Package for Motorola 88K Option Modiﬁcation Modifying Conﬁguration before InstallationPreparing the Hardware MVME187 Switches, Headers, Connectors, Fuses, and LEDs Eprom Location Jumper SettingsChecking the 187Bug EPROMs Eprom Orientation Optional Jumper Settings General Purpose Software Readable Header J1 J1 Bit Descriptions Factory Settings for J1 General Purpose Readable JumpersBit J1 Pins Description Header ConÞguration Jumpers Number Description Settings for J2 System Controller Header System Controller Header J2 Optional Sram Backup Power Source Select Header J6 Serial Port 4 Clock Conﬁguration Select Headers J7 and J8 Primary source VMEbus Number Description Action Preparing the MVME187 for InstallationMVME187 Preparation Procedure Step Action Chassis Preparation/Slot Selection ProcedurePreparing the System Chassis MVME187 Installation Procedure Installing the HardwareInstalling the MVME187 in the Chassis Transition Modules and Adapter Boards Overview Typical Internal Scsi and Serial Port Connections Equipment Type Connect Through Equipment Connections10. Peripheral Connections Installing Transition Modules and Adapter Boards Connecting Peripherals 12. Peripheral Connection Procedures Action Refer to Using MVME712A/AM and MVME712B Typical Transition Module Peripheral Port Connectors Starting the System Completing the Installation13. Installation Completion Procedure 14. System Startup Overview System Mode Powering Up the SystemIf 187Bug is Board Mode Initializing the Real-Time Clock Programming the PCCchip2 and VMEchip2 15. RTC Initialization ProcedureStep Action Board Mode System Mode System Considerations Backplane Power ConnectionsGlobal Bus Timeout Memory Address Ranges Ethernet LAN +12 Vdc Fuse Multiple Module Cage ConﬁgurationGcsr Location Monitor Register Scsi Bus Termination Storage and the Real-Time Clock Hardware Preparation and Installation Introduction to MVME187Bug Overview of M88000 Firmware Trap #496 Routines Command FacilitiesDescription of 187Bug Debugger or Diagnostic Directories Keyboard Control Comparison with M68000-Based Firmware 187Bug Implementation Booting and Restarting 187Bug Memory Requirements Starting Up 187Bug AutobootAutoboot Sequence ROMboot ROMboot Sequence Requirement Optionally, with the ENV command Network BootNetwork Boot Sequence Restarting the System Reset Abort Abort Sequence Break SYSFAIL* Assertion/Negation MPU Clock Speed Calculation Parameter Tables Disk I/O SupportDisk Support Facilities Supported Controllers Blocks Versus Sectors Device Probe Function Disk I/O via 187Bug Commands Disk I/O via 187Bug System Calls BH Bootstrap and HaltController Command Packets Default 187Bug Controller and Device Parameters These commands Status is Command Disk I/O Error CodesUsing When you invoke one Change BO or BH UDP/IP Protocol Modules Network I/O SupportIntel 82596 LAN Coprocessor Ethernet Driver RARP/ARP Protocol Modules Bootp Protocol ModuleNetwork Boot Control Module Tftp Protocol Module Multiprocessor Control Register Mpcr Method Network I/O Error CodesMultiprocessor Support Multiprocessor Address Register Mpar Mpcr Powerup SequenceMpcr Status Codes Multiprocessor Support Global Control and Status Register Gcsr Method Command Description PreÞx Diagnostic FacilitiesDiagnostic Monitor Commands/Preﬁxes Diagnostic Utilities Command Description Write loop enable Read loop enable 187Bug Diagnostic Test Groups Diagnostic Test Groups Debugger General Information Entering Debugger Command Lines Terminal Input/Output Control More characters to it. You can edit the line by Debugger Command Syntax Base IdentiÞer Examples Syntactic VariablesExpression as a Parameter Expression Result In Hex Address as a ParameterString Numeric Value Literal Address Formats Port Numbers Offset Registers Downloading an S-Record Object File Entering and Debugging ProgramsCreating a Program with the Assembler/Disassembler Calling System Utilities from User Programs Read the Program from Disk Preserving the Debugger Operating Environment 187Bug Vector Table and Workspace Exception Vectors Used by 187Bug Floating Point SupportHardware Functions CPU/MPU Registers Integer Data Types Floating Point Data Types Single Precision Real Double Precision Real Scientiﬁc Notation 187Bug Debugger Command Set Debugger Commands ENV D Cnfg I MCS range B H W IOI C L Nopa port Niot HAZn a Nopf port Time C L O RL addr B H WSYM addr VER E Cnfg IM This Appendix CoversConﬁguring the Board Information Block Configure and Environment Commands Setting Environment to Bug/Operating System Table A-1. ENV Command Parameters ENV Parameter and Options Default Meaning of Default First location tested when the Bug LUN Network Auto Boot ConÞguration Memory Search Ending Address Slave address decoders setup Guide Base address of the VMEbus resource This will be the local bus address Table A-1. ENV Command Parameters Configure and Environment Commands Address Disk/Tape Controller Modules SupportedController Type First Second Disk/Tape Controller Default Conﬁgurations $XXXXXXXX MVME327A -- 9 Devices Controller LUN Address Device LUN Device Type IOT Command Parameters for Supported Floppy Types IOT Parameter Floppy Types and Formats Other Characteristics Disk/Tape Controller Data Network Controller Modules Supported Table C-1. Network Controller Access DataDebugger Commands Debugger System Calls Address Interface $FFFFA400 Table D-1. Troubleshooting Steps Condition Possible Try This Problem Troubleshooting the MVME187 Solving Startup Problems Table D-1. Troubleshooting Steps Return Set mmddyyhhmm ReturnEnvd Return De Return Env ReturnSt Return Troubleshooting the MVME187 Solving Startup Problems EEIA-232-D Interconnections Introduction Pin Signal Name and DescriptionTable E-1. EIA-232-D Interconnections Number Mnemonic Signal Name and Description Number Mnemonic Levels of Implementation Signal Adaptations Sample Conﬁgurations Figure E-1. Middle-of-the-Road EIA-232-D Conﬁguration Figure E-2. Minimum EIA-232-D Connection Proper Grounding EIA-232-D Interconnections Index Bootp Default configurations B-2 IN-12 Local bus Local I/O devices 2-26VMEbus 2-28VMEbus short I/O IN-14 See also CD2401 scientific notation 5-14 Scon LED Nvram XON/XOFF