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Motorola MVME187 manual Network Boot Sequence

Models: MVME187

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Network Boot

4

Debugger General Information

For a user's ROMboot module to gain control through the

ROMboot linkage, four requirements must be met:

Requirement...	Optionally, with the ENV command...

Power must have just been	Change this to respond to any reset.
applied.

Your routine must be located	Change this to any other portion of the onboard
within the MVME187 ROM	memory, or even offboard VMEbus memory.
memory map.

The ASCII string ÒBOOTÓ must be located within the speciÞed memory range.

Your routine must pass a checksum test, which ensures that this routine was really intended to receive control at powerup.

For complete details on how to use ROMboot, refer to the Debugging Package for Motorola 88K RISC CPUs User's Manual.

Network Boot

Network Auto Boot is a software routine contained in the 187Bug EPROMs that provides a mechanism for booting an operating system using a network (local Ethernet interface) as the boot device.

Network Boot Sequence

1.The Network Auto Boot routine automatically scans for controllers and devices in a specified sequence until a valid bootable device containing a boot media is found or the list is exhausted.

2.If a valid bootable device is found, a boot from that device is started.

The controller scanning sequence goes from the lowest controller Logical Unit Number (LUN) detected to the highest LUN detected. (Refer to Appendix C for default LUNs.)

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Image 90

Motorola MVME187 manual Network Boot Sequence

Contents

MVME187 RISC Single Board Computer Installation Guide MVME187IG/D4Restricted Rights Legend Preface Use Caution When Exposing or Handling the CRT Safety Summary Safety Depends On YouDo Not Service or Adjust Alone Dangerous Procedure WarningsThis equipment generates, uses, and can radiate electro Page Contents Static RAM Optional SRAM Battery Backup Onboard DRAM Front Panel Switches and LEDs Data Bus StructureLocal Bus Arbitration M88000 MPU EPROM Programmable EPROM Features Battery Backed Up RAM and Clock VMEbus Interface I/O InterfacesCompleting the Installation 3-24 Starting the System Jumper Settings Optional Jumper SettingsInstalling the Hardware Installing the MVME187 in the Chassis Powering Up the System 3-25 Initializing the Real-Time ClockNetwork Boot Sequence 4-8 Restarting the System Reset Abort Break Booting and Restarting 187Bug 4-5 Starting Up 187Bug 4-6 AutobootAutoboot Sequence 4-6 ROMboot ROMboot Sequence 4-7 Network Boot BO Bootstrap Operating System 4-15 BH Bootstrap and HaltThe 187Bug Debugger Command Set 5-15 This Appendix Covers A-1 Multiprocessor Address Register MPAR 4-22 MPCR Powerup Sequence187Bug Diagnostic Test Groups 4-27 This Chapter Covers MPCR Status CodesSignal Adaptations E-4 Sample ConÞgurations E-4 Proper Grounding E-7 Using MVME712A/AM and MVME712B List of FiguresMVME187 General Block Diagram Typical Transition Module Peripheral Port ConnectorsList of Tables 1Introduction to the MVME187 Installation Guide This Chapter CoversAbout this Manual Signal Name Conventions Terminology, Conventions, and Deﬁnitions Used in this ManualData and Address Parameter Numeric Formats Assertion and Negation Conventions Data and Address Size DeﬁnitionsBig-Endian Byte Ordering Bit Value Descriptions Control and Status Bit DeﬁnitionsTrue/False Bit State Deﬁnitions The bit can be set and cleared under softwareRelated Documentation Document Set for MVME187-0xx BoardAdditional Manuals for this Board Other Applicable Motorola PublicationsAlso available but not included in the set Non-Motorola Peripheral Controllers Publications Bundle MC68230 Parallel Interface Timer PI/T Data Sheet Introduction to the MVME187 Installation GuideData Sheet Part NumberData, IEC 821 BUS Applicable Non-Motorola PublicationsANSI/IEEE Std Sheet, order numberIntroduction to the MVME187 Installation Guide 1-10Board Level Hardware Description General DescriptionThis Chapter Covers Onboard Memory Mezzanine Module SCSI Mass Storage InterfaceSerial Ports Parallel Printer PortEthernet Transceiver Interface Features 187Bug FirmwareFour 32-bit tick timers for periodic interrupts Watchdog timer Speciﬁcations Conformance to RequirementsTable 2-1. MVME187 General Speciﬁcations Board Level Overview ConnectorsFigure 2-1. MVME187 General Block Diagram AdaptersTransition Modules ASICsVMEchip2 ASIC Table 2-2. Bus TransfersPCCchip2 ASIC Functional Description MEMC040 Memory Controller ASICMCECC Memory Controller ASIC Front Panel Switches and LEDs Table 2-3. Front Panel SwitchesTable 2-4. Front Panel LEDs Data Bus Structure M88000 MPULocal Bus Arbitration Programmable EPROM Features EPROMStatic RAM Optional SRAM Battery Backup Onboard DRAM Stacking Mezzanines DRAM Programming ConsiderationsBattery Backed Up RAM and Clock VMEbus Interface I/O InterfacesSerial Port Interface Serial Interface Programming Considerations Parallel Port Interface Ethernet Interface Buffer Overruns SCSI InterfaceSCSI Termination Local Bus Timeout Programmable Tick TimersWatchdog Timer Local ResourcesMemory Maps Local Bus Memory MapNormal Address Range Devices Table 2-5. Local Bus Memory Map Table 2-6. Local I/O Devices Memory Map Table 2-6. Local I/O Devices Memory Map Continued VMEbus Accesses to the Local Bus VMEbus Memory MapVMEbus Short I/O Memory Map Hardware Preparation and Installation Unpacking the EquipmentThis Chapter Covers Overview of Startup Procedure Table 3-1. Startup OverviewComputer SCSI Software Table 3-1. Startup Overview Continuedobtain the Single Board UserÕs ManualTable 3-1. Startup Overview Continued pageobtain the Debugging Modifying Conﬁguration before Installation Preparing the HardwareOption Modiﬁcation Figure 3-1. MVME187 Switches, Headers, Connectors, Fuses, and LEDs MVMEEPROM Location Jumper SettingsChecking the 187Bug EPROMs EPROM OrientationOptional Jumper Settings General Purpose Software Readable Header J1Reserved/DeÞned Bits GPI0 - GPI3 Table 3-3. Factory Settings for J1 General Purpose Readable JumpersTable 3-2. J1 Bit Descriptions GPI4 - GPI7Table 3-4. Settings for J2 System Controller Header System Controller Header J2System Optional SRAM Backup Power Source Select Header J6 Serial Port 4 Clock Conﬁguration Select Headers J7 and J8Table 3-5. Settings for Optional J6 SRAM Backup Power Source Select HeaderSerial Port Table 3-6. Settings for J7 and J8 Serial Port 4 Clock ConﬁgurationSelect Headers clockPreparing the MVME187 for Installation Table 3-7. MVME187 Preparation ProcedureTable 3-8. Chassis Preparation/Slot Selection Procedure Preparing the System ChassisInstalling the Hardware Installing the MVME187 in the ChassisTable 3-9. MVME187 Installation Procedure Transition Modules and Adapter Boards Overview Installing the Hardware3-17 Figure 3-2. Typical Internal SCSI and Serial Port Connections Hardware Preparation and Installation3-18 Some connection diagrams are in the Single Board Computer Equipment ConnectionsTable 3-10. Peripheral Connections External SCSI drivesInstalling Transition Modules and Adapter Boards Connecting PeripheralsTable 3-11. Transition Module and Adapter Board Installation Overview baud rate 9600 baud default baud rate of MVME187 ports at Table 3-12. Peripheral Connection Proceduresparity disabled no parity powerupFigure 3-3. Using MVME712A/AM and MVME712B 712A Figure 3-4. Typical Transition Module Peripheral Port ConnectorsMVME To J10 onStarting the System Completing the InstallationTable 3-13. Installation Completion Procedure Table 3-14. System Startup OverviewExamining and/or Changing Environmental Parameters Powering Up the SystemInitializing the Real-Time Clock Board ModeSET MMddyyhhmm+/-CALC Table 3-15. RTC Initialization ProcedureProgramming the PCCchip2 and VMEchip2 187-BugSET 0522961037 ReturnSystem Considerations Backplane Power ConnectionsGlobal Bus Timeout Memory Address RangesMultiple Module Cage Conﬁguration GCSR Location Monitor RegisterEthernet LAN +12 Vdc Fuse SCSI Bus Termination Storage and the Real-Time Clock187-Bugps Return Hardware Preparation and Installation 3-30Overview of M88000 Firmware Debugger General InformationIntroduction to MVME187Bug This Chapter CoversCommand Facilities Description of 187BugTrap #496 Routines Debugger or Diagnostic Directories Keyboard ControlComparison with M68000-Based Firmware 187Bug ImplementationBooting and Restarting 187Bug Memory RequirementsAutoboot Autoboot SequenceStarting Up 187Bug ROMboot ROMboot SequenceNetwork Boot Network Boot SequenceRestarting the System During WARM reset ResetDuring COLD reset AbortAbort Sequence BreakBreak Sequence SYSFAIL* Assertion/NegationMPU Clock Speed Calculation Parameter Tables Disk I/O SupportDisk Support Facilities Supported ControllersBlocks Versus Sectors Device Probe FunctionIOI Input/Output Inquiry Disk I/O via 187Bug CommandsBO Bootstrap Operating System IOP Physical I/O to DiskBH Bootstrap and Halt Controller Command PacketsDisk I/O via 187Bug System Calls Default 187Bug Controller and Device Parameters Disk I/O Error Codes sourceNetwork I/O Support Intel 82596 LAN Coprocessor Ethernet DriverUDP/IP Protocol Modules RARP/ARP Protocol Modules BOOTP Protocol ModuleNetwork Boot Control Module TFTP Protocol ModuleNetwork I/O Error Codes Multiprocessor SupportMultiprocessor Control Register MPCR Method MPCR Powerup Sequence MPCR Status CodesMultiprocessor Address Register MPAR 3. As the initialization proceeds, the execution path comes to the prompt routine Global Control and Status Register GCSR Method Diagnostic Facilities Table 4-1. Diagnostic Monitor Commands/PreﬁxesCommand Table 4-2. Diagnostic UtilitiesTable 4-1. Diagnostic Monitor Commands/Preﬁxes Command187Bug Diagnostic Test Groups Table 4-3. Diagnostic Test GroupsDebugger General Information 4-28Terminal Input/Output Control Using the 187Bug DebuggerEntering Debugger Command Lines This Chapter CoversUsing the 187Bug Debugger Debugger Command Syntax Syntactic Variables Expression as a ParameterAddress as a Parameter Address Formats Port Numbers Offset RegistersEntering and Debugging Programs Creating a Program with the Assembler/DisassemblerDownloading an S-Record Object File Calling System Utilities from User Programs Read the Program from DiskPreserving the Debugger Operating Environment 187Bug Vector Table and WorkspaceException Vectors Used by 187Bug Floating Point SupportHardware Functions CPU/MPU Registers1. The sign field is the first field and is a binary field 2 hex digits. Bias = $7F Single Precision RealDouble Precision Real 3 hex digits. Bias = $3FFScientiﬁc Notation AS addr The 187Bug Debugger Command SetTable 5-1. Debugger Commands BC range del addr B H WDMA range del addr del vdir del am del blk Table 5-1. Debugger Commands ContinuedHE command DS addr count del addrdel device LUN del block # Table 5-1. Debugger Commands ContinuedMAW controller LUN MAR controller LUN del device LUNRS reg del exp del addr S D Table 5-1. Debugger Commands ContinuedSYMS symbol-name S SET mmddyyhhmm n CAConﬁgure and Environment Commands This Appendix CoversConﬁguring the Board Information Block Page Setting Environment to Bug/Operating System ENV DTable A-1. ENV Command Parameters The parameters to be configured are listed in the following tableTable A-1. ENV Command Parameters Continued FFBFFFFCTable A-1. ENV Command Parameters Continued Table A-1. ENV Command Parameters Continued Table A-1. ENV Command Parameters Continued FFFFCE0FTable A-1. ENV Command Parameters Continued 01FFFFFF01FF Table A-1. ENV Command Parameters ContinuedGuide FFE1FFFFTable A-1. ENV Command Parameters Continued EFFFFFFFTable A-1. ENV Command Parameters Continued Table A-1. ENV Command Parameters Continued Configure and Environment Commands A-14BDisk/Tape Controller Data Disk/Tape Controller Modules SupportedDisk/Tape Controller Default Conﬁgurations $XXXXXXXXMVME327A -- 9 Devices MVME328 -- 14 DevicesIOT Command Parameters for Supported Floppy Types MVME350 -- 1 DeviceFloppy Types and Formats Other CharacteristicsIOT Parameter DSDD5Disk/Tape Controller Data Table C-1. Network Controller Access Data CNetwork Controller DataNetwork Controller Modules Supported Table C-1. Network Controller Access Data Continued DTroubleshooting the MVME187 Solving Startup Problems Table D-1. Troubleshooting StepsTable D-1. Troubleshooting Steps Continued Table D-1. Troubleshooting Steps Continued III. Debug187-Diag Table D-1. Troubleshooting Steps Continued3. When prompted to Update Non-Volatile RAM, type in BREAKTable D-1. Troubleshooting Steps Continued Troubleshooting the MVME187 Solving Startup Problems EEIA-232-D Interconnections IntroductionTable E-1. EIA-232-D Interconnections GroundingLevels of Implementation Table E-1. EIA-232-D Interconnections ContinuedSignal Adaptations Sample ConﬁgurationsFigure E-1. Middle-of-the-Road EIA-232-D Conﬁguration Figure E-2. Minimum EIA-232-D Connection Proper Grounding EIA-232-D Interconnections Symbols IndexNumerics I N D E default configurations B-2 error codessupport via 187Bug commands 4-15 via 187Bug system calls I N D EI N D E local bus local I/O devices 2-26 VMEbus 2-28 VMEbus short I/O I N D EI N D E I N D E see also CD2401 scientific notation 5-14 SCON LEDI N D E in NVRAMedge significant 1-2 level significant see also CD2401 serial port 1 5-8 serial port 2I N D E