ST1, DA1, DA2, ST2 | Motorola TMS320C6711D manual

SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005

CPU (DSP core) description (continued)

Data Path A

Data Path B

		src1
	.L1†	src2
		dst	8
	long dst		8
	long dst		8
	long src		8
	long src		32
LD1 32 MSB			32
LD1 32 MSB
ST1			32	Register
	long src		32	Register
	long src		8	File A
	long dst		8	File A
	long dst		8	(A0−A15)
		dst		(A0−A15)
	.S1†

		src1
		src1
		src2
		dst
	.M1†	src1
		src2
LD1 32 LSB
		dst
DA1	.D1	src1
DA1		src2		2X
		src2

				1X
DA2		src2
DA2	.D2	src1
	.D2	src1
		dst
LD2 32 LSB
		src2
	.M2†	src1
		dst
		src2		Register
				Register
	.S2†	src1		File B
	.S2†	dst		(B0−B15)
		dst	8	(B0−B15)
	long dst		8
	long dst		8
	long src		8
	long src		32
LD2 32 MSB			32
LD2 32 MSB
ST2			32
	long src		32
	long src		8
	long dst		8
	long dst		8
		dst	8
	.L2†	dst
	.L2†	src2
		src2
		src1
				Control
				Register File

†In addition to fixed-point instructions, these functional units execute floating-point instructions.

Figure 1. TMS320C67x CPU (DSP Core) Data Paths

10	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Page 10

Image 10

Motorola TMS320C6711D warranty ST1, DA1, DA2, ST2

Contents

SPRS292A − October 2005 − Revised November Table of Contents Pages ADDITIONS/CHANGES/DELETIONS Revision HistoryMultichannel Buffered Serial Port Timing GDP and ZDP 272-PIN Ball Grid Array BGA PACKAGES† GDP and ZDP BGA packages bottom viewBottom View Description Hardware Features Internal Clock Device characteristicsCharacteristics of the C6711D Processor C6711D Device compatibility Functional block and CPU DSP core diagram Digital Signal Processor CPU DSP core description DA2 ST1DA1 ST2 TMS320C6711D Memory Map Summary Memory map summaryMemory Block Description Block Size Bytes HEX Address Range L2 Cache Registers Peripheral register descriptionsEmif Registers HEX Address Range Acronym Register Name Edma Parameter RAM† Interrupt Selector RegistersDevice Registers HEX Address Range Acronym Register Name Comments Edma Registers Quick DMA Qdma and Pseudo Registers† Gpio Registers PLL Controller RegistersHPI Registers McBSP0 and McBSP1 Registers Timer 0 and Timer 1 RegistersHEX Address Range Acronym Register Name Comments Timer McBSP0 McBSP1 Signal groups description CE1 CE3CE2 CE0 CLKOUT2/GP2 GpioGP7EXTINT7 GP6EXTINT6 GP5EXTINT5 GP4EXTINT4 General-Purpose Input/Output Gpio Port Device Configurations Device configurations at device reset BOOTMODE‡ Configuration GDP/ZDP Functional Description PINCLKMODE0 Eksrc Devcfg register descriptionBIT # Name Description Terminal Functions Terminal Functions PIN SignalIPD Description Name GDP IPU‡ ZDP Resets and Interrupts IPD Description Name GDP IPU‡ ZDP Jtag Emulation Little Endian IPD Description Name GDP IPU‡ ZDP HOST-PORT Interface HPIUsed for transfer of data, address, and control HD12 Decoded from the two lowest bits of the internal address Only one asserted during any external data accessEmif − ASYNCHRONOUS/SYNCHRONOUS Memory Control ¶ IPD Description Name GDP IPU‡ ZDP Emif − Address ¶ EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2 IPD Description Name GDP IPU‡ ZDP Emif − Data ¶ Multichannel Buffered Serial Port 1 McBSP1 Multichannel Buffered Serial Port 0 McBSP0 GENERAL-PURPOSE INPUT/OUTPUT Gpio Module RSV IPU RSVRSV IPD Cvdd Name GDP ZDP Supply Voltage PinsDvdd Supply voltage See Note VSS Description Name GDP ZDP Supply Voltage PinsGround Pins GND PIN Signal TYPE† Description Name GDP ZDP Ground Pins VSS Description Name GDP ZDP Ground Pins VSS GND Software Development Tools Development supportHardware Development Tools Device and development-support tool nomenclature Device supportFully qualified production device Device Speed Range Device Family Temperature Range Default 0 C to 90 CPrefix Technology Documentation support Pwrd CPU CSR register descriptionRevision ID PCC DCC Pgie GIE CPU ID CPU CSR Register Bit Field DescriptionPCC Ccfg Register Bit Field Description Cache configuration Ccfg register descriptionL2MODE DSP Interrupts Interrupt Selector DSP Interrupt Default Selector Module ControlInterrupt sources and interrupt selector Event Edma Channels Edma module and Edma selectorEdma Selector ESEL1 Register 0x01A0 FF04 ESEL3 Register 0x01A0 FF0C PLL and PLL controller Enabled or Disabled PLL Lock and Reset TimesClkout Signals, Default Settings, and Control MIN TYP MAX Unit PLL Clock Frequency Ranges†‡ Clock SignalGDPA−167, ZDPA-167 Pllcsr Register 0x01B7 C100 PLL Control/Status Register Pllcsr Pllm Register 0x01B7 C110 PLL Multiplier Control Register Pllm DxEN Oscillator Divider 1 Register OSCDIV1 OSCDIV1 Register 0x01B7 C124OD1EN GP7 GP6 GP5 GP4 GP2 General-purpose input/output GpioDIR Power-down mode logic Pwrd Field of the CSR Register PD3 PD2 PD1 System-level design considerations Power-supply sequencingCharacteristics of the Power-Down Modes Mode Dvdd Power-supply decouplingPower-supply design considerations DSP Cvdd VSS GND Ieee 1149.1 Jtag compatibility statement Emif device speed Example Boards and Maximum Emif Speed Emif Data Lines Pins Where Data Present Emif big endian mode correctnessED3124 BE3 ED2316 BE2 ED158 BE1 ED70 BE0 Bootmode Reset MIN NOM MAX Unit Recommended operating conditions‡IOH Parameter Test Conditions MIN TYP MAX Unit IOZ Tester Pin Electronics Signal transition levelsParameter Measurement Information Output Under Test AC transient rise/fall time specifications = 0.3 tcmax† VIL max VUS max Ground Timing parameters and board routing analysis Board-Level Timings Example see Figure Control Signals † Output from DSPOutput from DSP Timing requirements for Clkin †‡§ PLL Mode Bypass Mode UnitInput and Output Clocks See Figure Parameter GDPA-167Clkin CLKOUT3 −200 Timing requirements for ECLKIN† see FigureGDPA-167 ZDPA−167 −250 See −Figure Asynchronous Memory TimingTiming requirements for asynchronous memory cycles†‡§ Are AOE/SDRAS/SSOE † Setup = Strobe = Not ReadyCEx BE30 EA212 Address ED310 Read Data AWE/SDWE/SSWE † Ardy CEx BE30 EA212 Setup = Strobe = Not Ready Hold =AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy SYNCHRONOUS-BURST Memory Timing Timing requirements for synchronous-burst Sram cycles† EA212 ED310 CEx BE30BE1 BE2 BE3 BE4 ARE/SDCAS/SSADS† AOE/SDRAS/SSOE† AWE/SDWE/SSWE† Synchronous Dram Timing Timing requirements for synchronous Dram cycles† see Figure EA2113 Bank EA112 Column EA12 ED310 Read EclkoutAOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† EA12 ED310 Write EclkoutEA2113 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Actv EclkoutCEx BE30 EA2113 Bank Activate EA112 Row Address EA12 ED310 Dcab Eclkout Refr Eclkout Deac EclkoutCEx BE30 EA2113 Bank EA112 EA12 ED310 CEx BE30 EA212 EA12 ED310 MRS Eclkout CEx BE30 EA212 MRS value ED310 Timing requirements for See Figure HOLD/HOLDA cycles† HOLD/HOLDA TimingHold Holda Busreq Timing Eclkout Busreq Timing requirements for reset†‡ see Figure Reset TimingCLKMODE0 = Clkin Eclkin Reset PhaseEmif Z Group† Emif Low Group† Group 2† Boot and Device Timing requirements for external interrupts† see Figure External Interrupt TimingEXTINT, NMI Hstrobe HOST-PORT Interface TimingGDPA−167 Hstrobe Hrdy HCS Hrdy Has † HasHR/W Hhwil Hstrobe † HCS HR/W Hhwil Hstrobe ‡ HCS Hrdy HD150 input 1st halfword 2nd halfwordHD150 input 1st half-word 2nd half-word −1 ¶ Multichannel Buffered Serial Port Timing Bitn-1 Clks ClkrFSR int Clkx FSR external CLKR/X no need to resync CLKR/X needs resync Timing requirements for FSR when Gsync = 1 see FigureClks Master Slave MIN MAX Clkx FSX MASTER§ Slave MINBit Bitn-1 MASTER§ Slave MIN MAX GDPA-167 McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Timing requirements for timer inputs† Timer TimingTINPx TOUTx Timing requirements for Gpio inputs†‡ GENERAL-PURPOSE INPUT/OUTPUT Gpio Port TimingGPIx GPOx Timing requirements for Jtag test port see Figure DTCKL-TDOV Delay time, TCK low to TDO validJtag TEST-PORT Timing TCK TDO TDI/TMS/TRST Thermal resistance characteristics S-PBGA package for ZDP Package thermal resistance characteristicsThermal resistance characteristics S-PBGA package for GDP Mechanical Data MSL Peak Temp Orderable Device Status Package Pins Package Eco PlanPackaging Information Qty GDP S-PBGA-N272 Seating Plane 4204396/A 04/02 ZDP S-PBGA-N272 Seating Plane 4204398/A 04/02 Important Notice

SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005

CPU (DSP core) description (continued)

ST1

DA1

DA2

ST2

long src

long dst

dst

.L2†

Figure 1. TMS320C67x CPU (DSP Core) Data Paths