Synchronous Dram Timing | Motorola TMS320C6711D instruction

SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005

SYNCHRONOUS DRAM TIMING

timing requirements for synchronous DRAM cycles† (see Figure 31)

			GDPA-167
			ZDPA−167
NO.			−200			UNIT
			−250
			MIN		MAX

6	tsu(EDV-EKOH)	Setup time, read EDx valid before ECLKOUT high	1.5			ns
7	th(EKOH-EDV)	Hold time, read EDx valid after ECLKOUT high	2.5			ns

†The SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.

switching characteristics over recommended operating conditions for synchronous DRAM cycles†‡ (see Figure 31−Figure 37)

GDPA-167

ZDPA−167

NO.

PARAMETER

−200

UNIT

−250

MIN

MAX

1

td(EKOH-CEV)

Delay time, ECLKOUT high to

valid

1.5

7

ns

CEx

2

td(EKOH-BEV)

Delay time, ECLKOUT high to

valid

7

ns

BEx

3

td(EKOH-BEIV)

Delay time, ECLKOUT high to

invalid

1.5

ns

BEx

4

td(EKOH-EAV)

Delay time, ECLKOUT high to EAx valid

7

ns

5

td(EKOH-EAIV)

Delay time, ECLKOUT high to EAx invalid

1.5

ns

8

td(EKOH-CASV)

Delay time, ECLKOUT high to

1.5

7

ns

ARE/SDCAS/SSADS valid

9

td(EKOH-EDV)

Delay time, ECLKOUT high to

valid

7

ns

EDx

10

td(EKOH-EDIV)

Delay time, ECLKOUT high to

invalid

1.5

ns

EDx

11

td(EKOH-WEV)

Delay time, ECLKOUT high to

1.5

7

ns

AWE/SDWE/SSWE valid

12

td(EKOH-RAS)

Delay time, ECLKOUT high to,

1.5

7

ns

AOE/SDRAS/SSOE valid

†The SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.

‡ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses.

76	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Image 76

Motorola TMS320C6711D warranty Synchronous Dram Timing, Timing requirements for synchronous Dram cycles† see Figure

Contents

SPRS292A − October 2005 − Revised November Table of Contents Pages ADDITIONS/CHANGES/DELETIONS Revision HistoryMultichannel Buffered Serial Port Timing GDP and ZDP 272-PIN Ball Grid Array BGA PACKAGES† GDP and ZDP BGA packages bottom viewBottom View Description Device characteristics Characteristics of the C6711D ProcessorHardware Features Internal Clock C6711D Device compatibility Functional block and CPU DSP core diagram Digital Signal Processor CPU DSP core description ST1 DA1DA2 ST2 TMS320C6711D Memory Map Summary Memory map summaryMemory Block Description Block Size Bytes HEX Address Range Peripheral register descriptions Emif RegistersL2 Cache Registers HEX Address Range Acronym Register Name Interrupt Selector Registers Device RegistersEdma Parameter RAM† HEX Address Range Acronym Register Name Comments Edma Registers Quick DMA Qdma and Pseudo Registers† Gpio Registers PLL Controller RegistersHPI Registers Timer 0 and Timer 1 Registers HEX Address Range Acronym Register Name Comments TimerMcBSP0 and McBSP1 Registers McBSP0 McBSP1 Signal groups description CE3 CE2CE1 CE0 Gpio GP7EXTINT7 GP6EXTINT6 GP5EXTINT5 GP4EXTINT4CLKOUT2/GP2 General-Purpose Input/Output Gpio Port Device Configurations Device configurations at device reset BOOTMODE‡ Configuration GDP/ZDP Functional Description PINCLKMODE0 Eksrc Devcfg register descriptionBIT # Name Description Terminal Functions Terminal Functions PIN SignalIPD Description Name GDP IPU‡ ZDP Resets and Interrupts IPD Description Name GDP IPU‡ ZDP Jtag Emulation IPD Description Name GDP IPU‡ ZDP HOST-PORT Interface HPI Used for transfer of data, address, and controlLittle Endian HD12 Decoded from the two lowest bits of the internal address Only one asserted during any external data accessEmif − ASYNCHRONOUS/SYNCHRONOUS Memory Control ¶ IPD Description Name GDP IPU‡ ZDP Emif − Address ¶ EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2 IPD Description Name GDP IPU‡ ZDP Emif − Data ¶ Multichannel Buffered Serial Port 1 McBSP1 Multichannel Buffered Serial Port 0 McBSP0 GENERAL-PURPOSE INPUT/OUTPUT Gpio Module RSV IPU RSVRSV IPD Name GDP ZDP Supply Voltage Pins DvddCvdd Supply voltage See Note Description Name GDP ZDP Supply Voltage Pins Ground PinsVSS GND PIN Signal TYPE† Description Name GDP ZDP Ground Pins VSS Description Name GDP ZDP Ground Pins VSS GND Software Development Tools Development supportHardware Development Tools Device and development-support tool nomenclature Device supportFully qualified production device Device Family Temperature Range Default 0 C to 90 C PrefixDevice Speed Range Technology Documentation support CPU CSR register description Revision IDPwrd PCC DCC Pgie GIE CPU ID CPU CSR Register Bit Field DescriptionPCC Ccfg Register Bit Field Description Cache configuration Ccfg register descriptionL2MODE DSP Interrupt Default Selector Module Control Interrupt sources and interrupt selectorDSP Interrupts Interrupt Selector Event Edma Channels Edma module and Edma selectorEdma Selector ESEL1 Register 0x01A0 FF04 ESEL3 Register 0x01A0 FF0C PLL and PLL controller PLL Lock and Reset Times Clkout Signals, Default Settings, and ControlEnabled or Disabled MIN TYP MAX Unit PLL Clock Frequency Ranges†‡ Clock SignalGDPA−167, ZDPA-167 Pllcsr Register 0x01B7 C100 PLL Control/Status Register Pllcsr Pllm Register 0x01B7 C110 PLL Multiplier Control Register Pllm DxEN Oscillator Divider 1 Register OSCDIV1 OSCDIV1 Register 0x01B7 C124OD1EN GP7 GP6 GP5 GP4 GP2 General-purpose input/output GpioDIR Power-down mode logic Pwrd Field of the CSR Register PD3 PD2 PD1 Power-supply sequencing Characteristics of the Power-Down ModesSystem-level design considerations Mode Power-supply decoupling Power-supply design considerationsDvdd DSP Cvdd VSS GND Ieee 1149.1 Jtag compatibility statement Emif device speed Example Boards and Maximum Emif Speed Emif Data Lines Pins Where Data Present Emif big endian mode correctnessED3124 BE3 ED2316 BE2 ED158 BE1 ED70 BE0 Bootmode Reset MIN NOM MAX Unit Recommended operating conditions‡IOH Parameter Test Conditions MIN TYP MAX Unit IOZ Signal transition levels Parameter Measurement InformationTester Pin Electronics Output Under Test AC transient rise/fall time specifications = 0.3 tcmax† VIL max VUS max Ground Timing parameters and board routing analysis Board-Level Timings Example see Figure Control Signals † Output from DSPOutput from DSP PLL Mode Bypass Mode Unit Input and Output ClocksTiming requirements for Clkin †‡§ See Figure Parameter GDPA-167Clkin CLKOUT3 Timing requirements for ECLKIN† see Figure GDPA-167 ZDPA−167−200 −250 Asynchronous Memory Timing Timing requirements for asynchronous memory cycles†‡§See −Figure Are Setup = Strobe = Not Ready CEx BE30 EA212 Address ED310 Read DataAOE/SDRAS/SSOE † AWE/SDWE/SSWE † Ardy CEx BE30 EA212 Setup = Strobe = Not Ready Hold =AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy SYNCHRONOUS-BURST Memory Timing Timing requirements for synchronous-burst Sram cycles† CEx BE30 BE1 BE2 BE3 BE4EA212 ED310 ARE/SDCAS/SSADS† AOE/SDRAS/SSOE† AWE/SDWE/SSWE† Synchronous Dram Timing Timing requirements for synchronous Dram cycles† see Figure EA2113 Bank EA112 Column EA12 ED310 Read EclkoutAOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Write Eclkout EA2113EA12 ED310 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Actv Eclkout CEx BE30 EA2113 Bank Activate EA112 Row Address EA12 ED310AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Dcab Eclkout Deac Eclkout CEx BE30 EA2113 Bank EA112 EA12 ED310Refr Eclkout CEx BE30 EA212 EA12 ED310 MRS Eclkout CEx BE30 EA212 MRS value ED310 Timing requirements for See Figure HOLD/HOLDA cycles† HOLD/HOLDA TimingHold Holda Busreq Timing Eclkout Busreq Timing requirements for reset†‡ see Figure Reset TimingCLKMODE0 = Clkin Eclkin Reset PhaseEmif Z Group† Emif Low Group† Group 2† Boot and Device Timing requirements for external interrupts† see Figure External Interrupt TimingEXTINT, NMI HOST-PORT Interface Timing GDPA−167Hstrobe Hstrobe Hrdy HCS Hrdy Has HR/W Hhwil Hstrobe † HCSHas † HR/W Hhwil Hstrobe ‡ HCS Hrdy HD150 input 1st halfword 2nd halfwordHD150 input 1st half-word 2nd half-word −1 ¶ Multichannel Buffered Serial Port Timing Clks Clkr FSR intBitn-1 Clkx Timing requirements for FSR when Gsync = 1 see Figure ClksFSR external CLKR/X no need to resync CLKR/X needs resync Master Slave MIN MAX Clkx FSX MASTER§ Slave MINBit Bitn-1 MASTER§ Slave MIN MAX GDPA-167 McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Timing requirements for timer inputs† Timer TimingTINPx TOUTx Timing requirements for Gpio inputs†‡ GENERAL-PURPOSE INPUT/OUTPUT Gpio Port TimingGPIx GPOx DTCKL-TDOV Delay time, TCK low to TDO valid Jtag TEST-PORT TimingTiming requirements for Jtag test port see Figure TCK TDO TDI/TMS/TRST Package thermal resistance characteristics Thermal resistance characteristics S-PBGA package for GDPThermal resistance characteristics S-PBGA package for ZDP Mechanical Data Orderable Device Status Package Pins Package Eco Plan Packaging InformationMSL Peak Temp Qty GDP S-PBGA-N272 Seating Plane 4204396/A 04/02 ZDP S-PBGA-N272 Seating Plane 4204398/A 04/02 Important Notice