Busreq Timing, Eclkout Busreq | Motorola TMS320C6711D specs

SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005

BUSREQ TIMING

switching characteristics over recommended operating conditions for the BUSREQ cycles (see Figure 39)

		GDPA-167
		ZDPA−167
NO.	PARAMETER	−200		UNIT
		−250
		MIN	MAX

1	td(EKOH-BUSRV)Delay time, ECLKOUT high to BUSREQ valid	1.5	7.2	ns

ECLKOUT

BUSREQ

Figure 39. BUSREQ Timing

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

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Image 83

Motorola TMS320C6711D warranty Busreq Timing, Eclkout Busreq

Contents

SPRS292A − October 2005 − Revised November Table of Contents Multichannel Buffered Serial Port Timing Revision HistoryPages ADDITIONS/CHANGES/DELETIONS Bottom View GDP and ZDP BGA packages bottom viewGDP and ZDP 272-PIN Ball Grid Array BGA PACKAGES† Description C6711D Device characteristicsCharacteristics of the C6711D Processor Hardware Features Internal Clock Device compatibility Digital Signal Processor Functional block and CPU DSP core diagram CPU DSP core description ST2 ST1DA1 DA2 Memory Block Description Block Size Bytes HEX Address Range Memory map summaryTMS320C6711D Memory Map Summary HEX Address Range Acronym Register Name Peripheral register descriptionsEmif Registers L2 Cache Registers HEX Address Range Acronym Register Name Comments Interrupt Selector RegistersDevice Registers Edma Parameter RAM† Quick DMA Qdma and Pseudo Registers† Edma Registers HPI Registers PLL Controller RegistersGpio Registers McBSP0 McBSP1 Timer 0 and Timer 1 RegistersHEX Address Range Acronym Register Name Comments Timer McBSP0 and McBSP1 Registers Signal groups description CE0 CE3CE2 CE1 General-Purpose Input/Output Gpio Port GpioGP7EXTINT7 GP6EXTINT6 GP5EXTINT5 GP4EXTINT4 CLKOUT2/GP2 Device configurations at device reset Device Configurations CLKMODE0 Configuration GDP/ZDP Functional Description PINBOOTMODE‡ BIT # Name Description Devcfg register descriptionEksrc Terminal Functions IPD Description Name GDP IPU‡ ZDP PIN SignalTerminal Functions IPD Description Name GDP IPU‡ ZDP Jtag Emulation Resets and Interrupts HD12 IPD Description Name GDP IPU‡ ZDP HOST-PORT Interface HPIUsed for transfer of data, address, and control Little Endian Emif − ASYNCHRONOUS/SYNCHRONOUS Memory Control ¶ Only one asserted during any external data accessDecoded from the two lowest bits of the internal address EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2 IPD Description Name GDP IPU‡ ZDP Emif − Address ¶ Multichannel Buffered Serial Port 1 McBSP1 IPD Description Name GDP IPU‡ ZDP Emif − Data ¶ GENERAL-PURPOSE INPUT/OUTPUT Gpio Module Multichannel Buffered Serial Port 0 McBSP0 RSV IPD RSVRSV IPU Supply voltage See Note Name GDP ZDP Supply Voltage PinsDvdd Cvdd GND Description Name GDP ZDP Supply Voltage PinsGround Pins VSS VSS PIN Signal TYPE† Description Name GDP ZDP Ground Pins VSS GND Description Name GDP ZDP Ground Pins Hardware Development Tools Development supportSoftware Development Tools Fully qualified production device Device supportDevice and development-support tool nomenclature Technology Device Family Temperature Range Default 0 C to 90 CPrefix Device Speed Range Documentation support PCC DCC Pgie GIE CPU CSR register descriptionRevision ID Pwrd PCC CPU CSR Register Bit Field DescriptionCPU ID L2MODE Cache configuration Ccfg register descriptionCcfg Register Bit Field Description Event DSP Interrupt Default Selector Module ControlInterrupt sources and interrupt selector DSP Interrupts Interrupt Selector Edma Selector Edma module and Edma selectorEdma Channels ESEL3 Register 0x01A0 FF0C ESEL1 Register 0x01A0 FF04 PLL and PLL controller MIN TYP MAX Unit PLL Lock and Reset TimesClkout Signals, Default Settings, and Control Enabled or Disabled GDPA−167, ZDPA-167 Clock SignalPLL Clock Frequency Ranges†‡ PLL Control/Status Register Pllcsr Pllcsr Register 0x01B7 C100 PLL Multiplier Control Register Pllm Pllm Register 0x01B7 C110 DxEN OD1EN OSCDIV1 Register 0x01B7 C124Oscillator Divider 1 Register OSCDIV1 DIR General-purpose input/output GpioGP7 GP6 GP5 GP4 GP2 Power-down mode logic PD3 PD2 PD1 Pwrd Field of the CSR Register Mode Power-supply sequencingCharacteristics of the Power-Down Modes System-level design considerations DSP Cvdd VSS GND Power-supply decouplingPower-supply design considerations Dvdd Ieee 1149.1 Jtag compatibility statement Example Boards and Maximum Emif Speed Emif device speed ED3124 BE3 ED2316 BE2 ED158 BE1 ED70 BE0 Emif big endian mode correctnessEmif Data Lines Pins Where Data Present Reset Bootmode IOH Recommended operating conditions‡MIN NOM MAX Unit IOZ Parameter Test Conditions MIN TYP MAX Unit Output Under Test Signal transition levelsParameter Measurement Information Tester Pin Electronics = 0.3 tcmax† VIL max VUS max Ground AC transient rise/fall time specifications Timing parameters and board routing analysis Output from DSP Control Signals † Output from DSPBoard-Level Timings Example see Figure See Figure PLL Mode Bypass Mode UnitInput and Output Clocks Timing requirements for Clkin †‡§ Clkin CLKOUT3 GDPA-167Parameter −250 Timing requirements for ECLKIN† see FigureGDPA-167 ZDPA−167 −200 Are Asynchronous Memory TimingTiming requirements for asynchronous memory cycles†‡§ See −Figure AWE/SDWE/SSWE † Ardy Setup = Strobe = Not ReadyCEx BE30 EA212 Address ED310 Read Data AOE/SDRAS/SSOE † AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy Setup = Strobe = Not Ready Hold =CEx BE30 EA212 Timing requirements for synchronous-burst Sram cycles† SYNCHRONOUS-BURST Memory Timing ARE/SDCAS/SSADS† AOE/SDRAS/SSOE† AWE/SDWE/SSWE† CEx BE30BE1 BE2 BE3 BE4 EA212 ED310 Timing requirements for synchronous Dram cycles† see Figure Synchronous Dram Timing AOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Read EclkoutEA2113 Bank EA112 Column EA12 ED310 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Write EclkoutEA2113 EA12 ED310 Dcab Eclkout Actv EclkoutCEx BE30 EA2113 Bank Activate EA112 Row Address EA12 ED310 AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† CEx BE30 EA212 EA12 ED310 Deac EclkoutCEx BE30 EA2113 Bank EA112 EA12 ED310 Refr Eclkout CEx BE30 EA212 MRS value ED310 MRS Eclkout Hold Holda HOLD/HOLDA TimingTiming requirements for See Figure HOLD/HOLDA cycles† Eclkout Busreq Busreq Timing CLKMODE0 = Reset TimingTiming requirements for reset†‡ see Figure Emif Z Group† Emif Low Group† Group 2† Boot and Device PhaseClkin Eclkin Reset EXTINT, NMI External Interrupt TimingTiming requirements for external interrupts† see Figure Hstrobe Hrdy HOST-PORT Interface TimingGDPA−167 Hstrobe HCS Hrdy HR/W Hhwil Hstrobe ‡ HCS HasHR/W Hhwil Hstrobe † HCS Has † HD150 input 1st half-word 2nd half-word HD150 input 1st halfword 2nd halfwordHrdy −1 ¶ Multichannel Buffered Serial Port Timing Clkx Clks ClkrFSR int Bitn-1 Master Slave MIN MAX Timing requirements for FSR when Gsync = 1 see FigureClks FSR external CLKR/X no need to resync CLKR/X needs resync Bit Bitn-1 MASTER§ Slave MINClkx FSX MASTER§ Slave MIN MAX GDPA-167 McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = TINPx TOUTx Timer TimingTiming requirements for timer inputs† GPIx GPOx GENERAL-PURPOSE INPUT/OUTPUT Gpio Port TimingTiming requirements for Gpio inputs†‡ TCK TDO TDI/TMS/TRST DTCKL-TDOV Delay time, TCK low to TDO validJtag TEST-PORT Timing Timing requirements for Jtag test port see Figure Mechanical Data Package thermal resistance characteristicsThermal resistance characteristics S-PBGA package for GDP Thermal resistance characteristics S-PBGA package for ZDP Qty Orderable Device Status Package Pins Package Eco PlanPackaging Information MSL Peak Temp Seating Plane 4204396/A 04/02 GDP S-PBGA-N272 Seating Plane 4204398/A 04/02 ZDP S-PBGA-N272 Important Notice

SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005

BUSREQ TIMING

GDPA-167

PARAMETER

ECLKOUT

BUSREQ

Figure 39. BUSREQ Timing