Motorola TMS320C6711D warranty HD150 input 1st halfword 2nd halfword, Hrdy

SPRS292 − OCTOBER 2005

HOST-PORT INTERFACE TIMING (CONTINUED)

HAS	1		1
		2		2
HCNTL[1:0]
	1	2	1	2
HR/W
	1	2	1	2
HHWIL
		3	4	3
HSTROBE†			14
HCS
		12	13	12
				13
HD[15:0] (input)
		1st halfword	2nd halfword	17
	5			5
HRDY

†HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 44. HPI Write Timing (HAS Not Used, Tied High)

HAS†
	19	19
10	11	10	11
HCNTL[1:0]
10	11	10	11
HR/W
10	11	10	11
HHWIL
	3	4
HSTROBE‡		14
HCS	18		18
	12	13	12	13
HD[15:0] (input)
5	1st half-word	2nd half-word	17	5
HRDY

†For correct operation, strobe the HAS signal only once per HSTROBE active cycle.

‡ HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 45. HPI Write Timing (HAS Used)

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