SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
PLL and PLL controller (continued)
OSCDIV1 Register (0x01B7 C124)
31 |
| 28 | 27 | 24 | 23 |
| 20 | 19 |
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| 16 |
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| R−0 |
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15 | 14 | 12 |
| 8 |
| 5 | 4 |
| 2 | 1 | 0 |
11 | 7 | 3 | |||||||||
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OD1EN |
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| OSCDIV1 |
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R/W−1 |
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| R−0 |
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| R/W−0 0111 |
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Legend: R = Read only, R/W = Read/Write;
The OSCDIV1 register controls the oscillator divider 1 for CLKOUT3. The CLKOUT3 signal does not go through the PLL path.
Table 32. Oscillator Divider 1 Register (OSCDIV1)
BIT # | NAME |
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31:16 | Reserved | Reserved. | ||||||
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| Oscillator Divider 1 Enable. |
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15 | OD1EN | 0 | – | Oscillator Divider 1 Disabled. |
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| 1 | – | Oscillator Divider 1 Enabled (default). | ||||
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14:5 | Reserved | Reserved. | ||||||
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| Oscillator Divider 1 Ratio [default is /8 (0 0111)]. | ||||||
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| 00000 | = | /1 | 10000 | = | /17 | |
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| 00001 | = | /2 | 10001 | = | /18 | |
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| 00010 | = | /3 | 10010 | = | /19 | |
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| 00011 | = | /4 | 10011 | = | /20 | |
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| 00100 | = | /5 | 10100 | = | /21 | |
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| 00101 | = | /6 | 10101 | = | /22 | |
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| 00110 | = | /7 | 10110 | = | /23 | |
4:0 | OSCDIV1 | 00111 | = | /8 | 10111 | = | /24 | |
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| 01000 | = | /9 | 11000 | = | /25 | |
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| 01001 | = | /10 | 11001 | = | /26 | |
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| 01010 | = | /11 | 11010 | = | /27 | |
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| 01011 | = | /12 | 11011 | = | /28 | |
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| 01100 | = | /13 | 11100 | = | /29 | |
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| 01101 | = | /14 | 11101 | = | /30 | |
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| 01110 | = | /15 | 11110 | = | /31 | |
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| 01111 | = | /16 | 11111 | = | /32 | |
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