Motorola TMS320C6711D warranty MASTER§ Slave MIN MAX

SPRS292 − OCTOBER 2005

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡						(see Figure 49)
			GDPA−167
			ZDPA−167
NO.				−200			UNIT
				−250
			MASTER		SLAVE
			MIN MAX		MIN	MAX
4	tsu(DRV-CKXH)	Setup time, DR valid before CLKX high	12		2 − 6P		ns
5	th(CKXH-DRV)	Hold time, DR valid after CLKX high	4		5 + 12P		ns

†P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 49)

				GDPA−167
				ZDPA−167
NO.		PARAMETER			−200			UNIT
					−250
			MASTER§			SLAVE
			MIN	MAX		MIN	MAX
1	th(CKXL-FXL)	Hold time, FSX low after CLKX	L − 2	L + 3				ns
		¶
		low
2	t	Delay time, FSX low to CLKX high#	T − 2	T + 3				ns
	d(FXL-CKXH)
3	td(CKXL-DXV)	Delay time, CLKX low to DX valid	−3	4		6P + 2	10P + 17	ns
		Disable time, DX high
6	tdis(CKXL-DXHZ)	impedance following last data bit	−2	4		6P + 3	10P + 17	ns
		from CLKX low
7	td(FXL-DXV)	Delay time, FSX low to DX valid	H − 2	H + 6.5		4P + 2	8P + 17	ns

†P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)

=Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T =	CLKX period = (1 + CLKGDV) * S
H =	CLKX high pulse width	= (CLKGDV/2 + 1) * S if CLKGDV is even
		= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L =	CLKX low pulse width	= (CLKGDV/2) * S if CLKGDV is even

=(CLKGDV + 1)/2 * S if CLKGDV is odd or zero

¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

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