Device Configurations | Motorola TMS320C6711D manual

SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005

DEVICE CONFIGURATIONS

On this device, bootmode and certain device configurations/peripheral selections are determined at device reset. Also, other device configurations (e.g., EMIF input clock source) are software-configurable via the device configurations register (DEVCFG) [address location 0x019C0200] after device reset.

device configurations at device reset

Table 15 describes the C6711D device configuration pins, which are set up via internal or external pullup/pulldown resistors through the HPI data pins (HD[4:3], HD8, HD12) and CLKMODE0 pin. These configuration pins must be in the desired state until reset is released.

For proper device operation, do not oppose the internal pulldowns/pullups in the HD [14, 13, 11:9, 7, 1, 0] pins with the external pullups/pulldowns or by driving them at reset.

For more details on these device configuration pins, see the Terminal Functions table of this data sheet.

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Motorola TMS320C6711D warranty Device Configurations, Device configurations at device reset

Contents

SPRS292A − October 2005 − Revised November Table of Contents Multichannel Buffered Serial Port Timing Revision HistoryPages ADDITIONS/CHANGES/DELETIONS Bottom View GDP and ZDP BGA packages bottom viewGDP and ZDP 272-PIN Ball Grid Array BGA PACKAGES† Description Device characteristics Characteristics of the C6711D ProcessorHardware Features Internal Clock C6711D Device compatibility Functional block and CPU DSP core diagram Digital Signal Processor CPU DSP core description ST1 DA1DA2 ST2 Memory Block Description Block Size Bytes HEX Address Range Memory map summaryTMS320C6711D Memory Map Summary Peripheral register descriptions Emif RegistersL2 Cache Registers HEX Address Range Acronym Register Name Interrupt Selector Registers Device RegistersEdma Parameter RAM† HEX Address Range Acronym Register Name Comments Edma Registers Quick DMA Qdma and Pseudo Registers† HPI Registers PLL Controller RegistersGpio Registers Timer 0 and Timer 1 Registers HEX Address Range Acronym Register Name Comments TimerMcBSP0 and McBSP1 Registers McBSP0 McBSP1 Signal groups description CE3 CE2CE1 CE0 Gpio GP7EXTINT7 GP6EXTINT6 GP5EXTINT5 GP4EXTINT4CLKOUT2/GP2 General-Purpose Input/Output Gpio Port Device Configurations Device configurations at device reset CLKMODE0 Configuration GDP/ZDP Functional Description PINBOOTMODE‡ BIT # Name Description Devcfg register descriptionEksrc Terminal Functions IPD Description Name GDP IPU‡ ZDP PIN SignalTerminal Functions Resets and Interrupts IPD Description Name GDP IPU‡ ZDP Jtag Emulation IPD Description Name GDP IPU‡ ZDP HOST-PORT Interface HPI Used for transfer of data, address, and controlLittle Endian HD12 Emif − ASYNCHRONOUS/SYNCHRONOUS Memory Control ¶ Only one asserted during any external data accessDecoded from the two lowest bits of the internal address IPD Description Name GDP IPU‡ ZDP Emif − Address ¶ EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2 IPD Description Name GDP IPU‡ ZDP Emif − Data ¶ Multichannel Buffered Serial Port 1 McBSP1 Multichannel Buffered Serial Port 0 McBSP0 GENERAL-PURPOSE INPUT/OUTPUT Gpio Module RSV IPD RSVRSV IPU Name GDP ZDP Supply Voltage Pins DvddCvdd Supply voltage See Note Description Name GDP ZDP Supply Voltage Pins Ground PinsVSS GND PIN Signal TYPE† Description Name GDP ZDP Ground Pins VSS Description Name GDP ZDP Ground Pins VSS GND Hardware Development Tools Development supportSoftware Development Tools Fully qualified production device Device supportDevice and development-support tool nomenclature Device Family Temperature Range Default 0 C to 90 C PrefixDevice Speed Range Technology Documentation support CPU CSR register description Revision IDPwrd PCC DCC Pgie GIE PCC CPU CSR Register Bit Field DescriptionCPU ID L2MODE Cache configuration Ccfg register descriptionCcfg Register Bit Field Description DSP Interrupt Default Selector Module Control Interrupt sources and interrupt selectorDSP Interrupts Interrupt Selector Event Edma Selector Edma module and Edma selectorEdma Channels ESEL1 Register 0x01A0 FF04 ESEL3 Register 0x01A0 FF0C PLL and PLL controller PLL Lock and Reset Times Clkout Signals, Default Settings, and ControlEnabled or Disabled MIN TYP MAX Unit GDPA−167, ZDPA-167 Clock SignalPLL Clock Frequency Ranges†‡ Pllcsr Register 0x01B7 C100 PLL Control/Status Register Pllcsr Pllm Register 0x01B7 C110 PLL Multiplier Control Register Pllm DxEN OD1EN OSCDIV1 Register 0x01B7 C124Oscillator Divider 1 Register OSCDIV1 DIR General-purpose input/output GpioGP7 GP6 GP5 GP4 GP2 Power-down mode logic Pwrd Field of the CSR Register PD3 PD2 PD1 Power-supply sequencing Characteristics of the Power-Down ModesSystem-level design considerations Mode Power-supply decoupling Power-supply design considerationsDvdd DSP Cvdd VSS GND Ieee 1149.1 Jtag compatibility statement Emif device speed Example Boards and Maximum Emif Speed ED3124 BE3 ED2316 BE2 ED158 BE1 ED70 BE0 Emif big endian mode correctnessEmif Data Lines Pins Where Data Present Bootmode Reset IOH Recommended operating conditions‡MIN NOM MAX Unit Parameter Test Conditions MIN TYP MAX Unit IOZ Signal transition levels Parameter Measurement InformationTester Pin Electronics Output Under Test AC transient rise/fall time specifications = 0.3 tcmax† VIL max VUS max Ground Timing parameters and board routing analysis Output from DSP Control Signals † Output from DSPBoard-Level Timings Example see Figure PLL Mode Bypass Mode Unit Input and Output ClocksTiming requirements for Clkin †‡§ See Figure Clkin CLKOUT3 GDPA-167Parameter Timing requirements for ECLKIN† see Figure GDPA-167 ZDPA−167−200 −250 Asynchronous Memory Timing Timing requirements for asynchronous memory cycles†‡§See −Figure Are Setup = Strobe = Not Ready CEx BE30 EA212 Address ED310 Read DataAOE/SDRAS/SSOE † AWE/SDWE/SSWE † Ardy AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy Setup = Strobe = Not Ready Hold =CEx BE30 EA212 SYNCHRONOUS-BURST Memory Timing Timing requirements for synchronous-burst Sram cycles† CEx BE30 BE1 BE2 BE3 BE4EA212 ED310 ARE/SDCAS/SSADS† AOE/SDRAS/SSOE† AWE/SDWE/SSWE† Synchronous Dram Timing Timing requirements for synchronous Dram cycles† see Figure AOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Read EclkoutEA2113 Bank EA112 Column EA12 ED310 Write Eclkout EA2113EA12 ED310 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Actv Eclkout CEx BE30 EA2113 Bank Activate EA112 Row Address EA12 ED310AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Dcab Eclkout Deac Eclkout CEx BE30 EA2113 Bank EA112 EA12 ED310Refr Eclkout CEx BE30 EA212 EA12 ED310 MRS Eclkout CEx BE30 EA212 MRS value ED310 Hold Holda HOLD/HOLDA TimingTiming requirements for See Figure HOLD/HOLDA cycles† Busreq Timing Eclkout Busreq CLKMODE0 = Reset TimingTiming requirements for reset†‡ see Figure Emif Z Group† Emif Low Group† Group 2† Boot and Device PhaseClkin Eclkin Reset EXTINT, NMI External Interrupt TimingTiming requirements for external interrupts† see Figure HOST-PORT Interface Timing GDPA−167Hstrobe Hstrobe Hrdy HCS Hrdy Has HR/W Hhwil Hstrobe † HCSHas † HR/W Hhwil Hstrobe ‡ HCS HD150 input 1st half-word 2nd half-word HD150 input 1st halfword 2nd halfwordHrdy −1 ¶ Multichannel Buffered Serial Port Timing Clks Clkr FSR intBitn-1 Clkx Timing requirements for FSR when Gsync = 1 see Figure ClksFSR external CLKR/X no need to resync CLKR/X needs resync Master Slave MIN MAX Bit Bitn-1 MASTER§ Slave MINClkx FSX MASTER§ Slave MIN MAX GDPA-167 McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = TINPx TOUTx Timer TimingTiming requirements for timer inputs† GPIx GPOx GENERAL-PURPOSE INPUT/OUTPUT Gpio Port TimingTiming requirements for Gpio inputs†‡ DTCKL-TDOV Delay time, TCK low to TDO valid Jtag TEST-PORT TimingTiming requirements for Jtag test port see Figure TCK TDO TDI/TMS/TRST Package thermal resistance characteristics Thermal resistance characteristics S-PBGA package for GDPThermal resistance characteristics S-PBGA package for ZDP Mechanical Data Orderable Device Status Package Pins Package Eco Plan Packaging InformationMSL Peak Temp Qty GDP S-PBGA-N272 Seating Plane 4204396/A 04/02 ZDP S-PBGA-N272 Seating Plane 4204398/A 04/02 Important Notice