Clks Clkr, FSR int, Bitn-1, Clkx | Motorola TMS320C6711D specs

SPRS292 − OCTOBER 2005

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

CLKS
	1
	2
	3
	3
CLKR
	4
	4
FSR (int)
	5
	6
FSR (ext)
	7	8
		8
DR	Bit(n-1)	(n-2)	(n-3)
	2
	3
CLKX	3
CLKX
	9
FSX (int)

FSX (ext) FSX (XDATDLY=00b)

	13	14	13
	12	13
DX	Bit 0	Bit(n-1)	(n-2)	(n-3)

Figure 46. McBSP Timings

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Image 93

Motorola TMS320C6711D warranty Clks Clkr, FSR int, Clkx, FSX int FSX ext FSX XDATDLY=00b Bit Bitn-1

Contents

SPRS292A − October 2005 − Revised November Table of Contents Revision History Pages ADDITIONS/CHANGES/DELETIONSMultichannel Buffered Serial Port Timing GDP and ZDP BGA packages bottom view GDP and ZDP 272-PIN Ball Grid Array BGA PACKAGES†Bottom View Description Characteristics of the C6711D Processor Device characteristicsHardware Features Internal Clock C6711D Device compatibility Digital Signal Processor Functional block and CPU DSP core diagram CPU DSP core description DA1 ST1DA2 ST2 Memory map summary TMS320C6711D Memory Map SummaryMemory Block Description Block Size Bytes HEX Address Range Emif Registers Peripheral register descriptionsL2 Cache Registers HEX Address Range Acronym Register Name Device Registers Interrupt Selector RegistersEdma Parameter RAM† HEX Address Range Acronym Register Name Comments Quick DMA Qdma and Pseudo Registers† Edma Registers PLL Controller Registers Gpio RegistersHPI Registers HEX Address Range Acronym Register Name Comments Timer Timer 0 and Timer 1 RegistersMcBSP0 and McBSP1 Registers McBSP0 McBSP1 Signal groups description CE2 CE3CE1 CE0 GP7EXTINT7 GP6EXTINT6 GP5EXTINT5 GP4EXTINT4 GpioCLKOUT2/GP2 General-Purpose Input/Output Gpio Port Device configurations at device reset Device Configurations Configuration GDP/ZDP Functional Description PIN BOOTMODE‡CLKMODE0 Devcfg register description EksrcBIT # Name Description Terminal Functions PIN Signal Terminal FunctionsIPD Description Name GDP IPU‡ ZDP IPD Description Name GDP IPU‡ ZDP Jtag Emulation Resets and Interrupts Used for transfer of data, address, and control IPD Description Name GDP IPU‡ ZDP HOST-PORT Interface HPILittle Endian HD12 Only one asserted during any external data access Decoded from the two lowest bits of the internal addressEmif − ASYNCHRONOUS/SYNCHRONOUS Memory Control ¶ EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2 IPD Description Name GDP IPU‡ ZDP Emif − Address ¶ Multichannel Buffered Serial Port 1 McBSP1 IPD Description Name GDP IPU‡ ZDP Emif − Data ¶ GENERAL-PURPOSE INPUT/OUTPUT Gpio Module Multichannel Buffered Serial Port 0 McBSP0 RSV RSV IPURSV IPD Dvdd Name GDP ZDP Supply Voltage PinsCvdd Supply voltage See Note Ground Pins Description Name GDP ZDP Supply Voltage PinsVSS GND VSS PIN Signal TYPE† Description Name GDP ZDP Ground Pins VSS GND Description Name GDP ZDP Ground Pins Development support Software Development ToolsHardware Development Tools Device support Device and development-support tool nomenclatureFully qualified production device Prefix Device Family Temperature Range Default 0 C to 90 CDevice Speed Range Technology Documentation support Revision ID CPU CSR register descriptionPwrd PCC DCC Pgie GIE CPU CSR Register Bit Field Description CPU IDPCC Cache configuration Ccfg register description Ccfg Register Bit Field DescriptionL2MODE Interrupt sources and interrupt selector DSP Interrupt Default Selector Module ControlDSP Interrupts Interrupt Selector Event Edma module and Edma selector Edma ChannelsEdma Selector ESEL3 Register 0x01A0 FF0C ESEL1 Register 0x01A0 FF04 PLL and PLL controller Clkout Signals, Default Settings, and Control PLL Lock and Reset TimesEnabled or Disabled MIN TYP MAX Unit Clock Signal PLL Clock Frequency Ranges†‡GDPA−167, ZDPA-167 PLL Control/Status Register Pllcsr Pllcsr Register 0x01B7 C100 PLL Multiplier Control Register Pllm Pllm Register 0x01B7 C110 DxEN OSCDIV1 Register 0x01B7 C124 Oscillator Divider 1 Register OSCDIV1OD1EN General-purpose input/output Gpio GP7 GP6 GP5 GP4 GP2DIR Power-down mode logic PD3 PD2 PD1 Pwrd Field of the CSR Register Characteristics of the Power-Down Modes Power-supply sequencingSystem-level design considerations Mode Power-supply design considerations Power-supply decouplingDvdd DSP Cvdd VSS GND Ieee 1149.1 Jtag compatibility statement Example Boards and Maximum Emif Speed Emif device speed Emif big endian mode correctness Emif Data Lines Pins Where Data PresentED3124 BE3 ED2316 BE2 ED158 BE1 ED70 BE0 Reset Bootmode Recommended operating conditions‡ MIN NOM MAX UnitIOH IOZ Parameter Test Conditions MIN TYP MAX Unit Parameter Measurement Information Signal transition levelsTester Pin Electronics Output Under Test = 0.3 tcmax† VIL max VUS max Ground AC transient rise/fall time specifications Timing parameters and board routing analysis Control Signals † Output from DSP Board-Level Timings Example see FigureOutput from DSP Input and Output Clocks PLL Mode Bypass Mode UnitTiming requirements for Clkin †‡§ See Figure GDPA-167 ParameterClkin CLKOUT3 GDPA-167 ZDPA−167 Timing requirements for ECLKIN† see Figure−200 −250 Timing requirements for asynchronous memory cycles†‡§ Asynchronous Memory TimingSee −Figure Are CEx BE30 EA212 Address ED310 Read Data Setup = Strobe = Not ReadyAOE/SDRAS/SSOE † AWE/SDWE/SSWE † Ardy Setup = Strobe = Not Ready Hold = CEx BE30 EA212AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy Timing requirements for synchronous-burst Sram cycles† SYNCHRONOUS-BURST Memory Timing BE1 BE2 BE3 BE4 CEx BE30EA212 ED310 ARE/SDCAS/SSADS† AOE/SDRAS/SSOE† AWE/SDWE/SSWE† Timing requirements for synchronous Dram cycles† see Figure Synchronous Dram Timing Read Eclkout EA2113 Bank EA112 Column EA12 ED310AOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† EA2113 Write EclkoutEA12 ED310 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † CEx BE30 EA2113 Bank Activate EA112 Row Address EA12 ED310 Actv EclkoutAOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Dcab Eclkout CEx BE30 EA2113 Bank EA112 EA12 ED310 Deac EclkoutRefr Eclkout CEx BE30 EA212 EA12 ED310 CEx BE30 EA212 MRS value ED310 MRS Eclkout HOLD/HOLDA Timing Timing requirements for See Figure HOLD/HOLDA cycles†Hold Holda Eclkout Busreq Busreq Timing Reset Timing Timing requirements for reset†‡ see FigureCLKMODE0 = Phase Clkin Eclkin ResetEmif Z Group† Emif Low Group† Group 2† Boot and Device External Interrupt Timing Timing requirements for external interrupts† see FigureEXTINT, NMI GDPA−167 HOST-PORT Interface TimingHstrobe Hstrobe Hrdy HCS Hrdy HR/W Hhwil Hstrobe † HCS HasHas † HR/W Hhwil Hstrobe ‡ HCS HD150 input 1st halfword 2nd halfword HrdyHD150 input 1st half-word 2nd half-word −1 ¶ Multichannel Buffered Serial Port Timing FSR int Clks ClkrBitn-1 Clkx Clks Timing requirements for FSR when Gsync = 1 see FigureFSR external CLKR/X no need to resync CLKR/X needs resync Master Slave MIN MAX MASTER§ Slave MIN Clkx FSXBit Bitn-1 MASTER§ Slave MIN MAX GDPA-167 McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Timer Timing Timing requirements for timer inputs†TINPx TOUTx GENERAL-PURPOSE INPUT/OUTPUT Gpio Port Timing Timing requirements for Gpio inputs†‡GPIx GPOx Jtag TEST-PORT Timing DTCKL-TDOV Delay time, TCK low to TDO validTiming requirements for Jtag test port see Figure TCK TDO TDI/TMS/TRST Thermal resistance characteristics S-PBGA package for GDP Package thermal resistance characteristicsThermal resistance characteristics S-PBGA package for ZDP Mechanical Data Packaging Information Orderable Device Status Package Pins Package Eco PlanMSL Peak Temp Qty Seating Plane 4204396/A 04/02 GDP S-PBGA-N272 Seating Plane 4204398/A 04/02 ZDP S-PBGA-N272 Important Notice

Motorola TMS320C6711D warranty Clks Clkr, FSR int, Bitn-1, Clkx

Models: TMS320C6711D

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

CLKS

CLKR

FSR (int)

Bit(n-1)

CLKX

FSX (int)

FSX (ext) FSX (XDATDLY=00b)

Bit 0

Bit(n-1)

Figure 46. McBSP Timings