SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005

ASYNCHRONOUS MEMORY TIMING

timing requirements for asynchronous memory cycles†‡§

(see Figure 27−Figure 28)

 

 

 

 

 

 

 

 

 

 

GDPA-167

 

 

 

 

 

 

 

 

 

ZDPA−167

 

NO.

 

 

 

 

 

 

 

−200

 

UNIT

 

 

 

 

 

 

 

 

−250

 

 

 

 

 

 

 

 

 

 

MIN

MAX

 

 

 

 

 

 

 

 

 

 

3

tsu(EDV-AREH)

Setup time, EDx valid before

 

 

high

 

6.5

 

ns

ARE

 

 

4

th(AREH-EDV)

Hold time, EDx valid after

 

 

high

 

1

 

ns

ARE

 

 

6

tsu(ARDY-EKOH)

Setup time, ARDY valid before ECLKOUT high

 

3

 

ns

7

th(EKOH-ARDY)

Hold time, ARDY valid after ECLKOUT high

 

2.3

 

ns

To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is recognized in the cycle for which the setup and hold time is met. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met.

RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers.

§ E = ECLKOUT period in ns

switching characteristics over recommended operating conditions for asynchronous memory cycles†‡§ (see Figure 27–Figure 28)

 

 

 

 

 

 

 

 

 

 

 

 

 

GDPA-167

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ZDPA−167

 

 

NO.

 

 

PARAMETER

−200

 

UNIT

 

 

 

 

 

 

 

 

 

 

 

 

 

−250

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MIN

MAX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

tosu(SELV-AREL)

Output setup time, select signals valid to

 

 

low

RS*E − 1.7

 

ns

ARE

 

 

2

toh(AREH-SELIV)

Output hold time,

 

 

high to select signals invalid

RH*E − 1.7

 

ns

ARE

 

 

5

td(EKOH-AREV)

Delay time, ECLKOUT high to

 

 

valid

1.5

7

ns

ARE

 

8

tosu(SELV-AWEL)

Output setup time, select signals valid to

 

 

low

WS*E − 1.7

 

ns

AWE

 

9

toh(AWEH-SELIV)

Output hold time,

 

 

high to select signals and EDx invalid

WH*E − 1.7

 

ns

AWE

 

10

td(EKOH-AWEV)

Delay time, ECLKOUT high to

 

 

valid

1.5

7

ns

AWE

 

 

 

 

 

 

 

 

 

 

 

 

 

(WS−1)*E −

 

 

11

tosu(EDV-AWEL)

Output setup time, ED valid to AWE low

 

ns

1.7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers.

E = ECLKOUT period in ns

§ Select signals include: CEx, BE[3:0], EA[21:2], and AOE.

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

71

Page 71
Image 71
Motorola TMS320C6711D Asynchronous Memory Timing, Timing requirements for asynchronous memory cycles†‡§, See −Figure, Are