SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
ASYNCHRONOUS MEMORY TIMING
timing requirements for asynchronous memory cycles†‡§ | (see Figure 27−Figure 28) |
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| ZDPA−167 |
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NO. |
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| −200 |
| UNIT |
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| −250 |
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| MIN | MAX |
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3 | Setup time, EDx valid before |
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| 6.5 |
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ARE |
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4 | Hold time, EDx valid after |
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| 1 |
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ARE |
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6 | Setup time, ARDY valid before ECLKOUT high |
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7 | Hold time, ARDY valid after ECLKOUT high |
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†To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is recognized in the cycle for which the setup and hold time is met. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met.
‡RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers.
§ E = ECLKOUT period in ns
switching characteristics over recommended operating conditions for asynchronous memory cycles†‡§ (see Figure
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| ZDPA−167 |
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NO. |
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| PARAMETER | −200 |
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| −250 |
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| MIN | MAX |
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1 | Output setup time, select signals valid to |
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| low | RS*E − 1.7 |
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ARE |
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2 | Output hold time, |
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| high to select signals invalid | RH*E − 1.7 |
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ARE |
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5 | Delay time, ECLKOUT high to |
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| valid | 1.5 | 7 | ns | ||||||||
ARE |
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8 | Output setup time, select signals valid to |
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| low | WS*E − 1.7 |
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AWE |
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9 | Output hold time, |
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| high to select signals and EDx invalid | WH*E − 1.7 |
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AWE |
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10 | Delay time, ECLKOUT high to |
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| valid | 1.5 | 7 | ns | ||||||||
AWE | |||||||||||||||
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| (WS−1)*E − |
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11 | Output setup time, ED valid to AWE low |
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1.7 |
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†RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers.
‡ E = ECLKOUT period in ns
§ Select signals include: CEx, BE[3:0], EA[21:2], and AOE.
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 | 71 |