SPRS292 − OCTOBER 2005

switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 50)

 

 

 

 

GDPA−167

 

 

 

 

 

 

ZDPA−167

 

 

NO.

 

PARAMETER

 

 

−200

 

UNIT

 

 

 

−250

 

 

 

 

 

 

 

 

 

 

MASTER§

SLAVE

 

 

 

 

MIN

MAX

MIN

MAX

 

 

 

 

 

 

 

 

 

1

th(CKXH-FXL)

Hold time, FSX low

T − 2

T + 3

 

 

ns

after CLKX high

 

 

2

td(FXL-CKXL)

Delay time, FSX low to CLKX low#

H − 2

H + 3

 

 

ns

3

td(CKXL-DXV)

Delay time, CLKX low to DX valid

−3

4

6P + 2

10P + 17

ns

6

tdis(CKXH-DXHZ)

Disable time, DX high impedance following last data bit from

H − 2

H + 3

 

 

ns

CLKX high

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

tdis(FXH-DXHZ)

Disable time, DX high impedance following last data bit from FSX

 

 

2P + 3

6P + 17

ns

high

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

td(FXL-DXV)

Delay time, FSX low to DX valid

 

 

4P + 2

8P + 17

ns

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)

=Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T =

CLKX period = (1 + CLKGDV) * S

H =

CLKX high pulse width

= (CLKGDV/2 + 1) * S if CLKGDV is even

 

 

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L =

CLKX low pulse width

= (CLKGDV/2) * S if CLKGDV is even

=(CLKGDV + 1)/2 * S if CLKGDV is odd or zero

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

CLKX

 

 

 

 

 

 

1

2

 

 

 

FSX

 

 

 

 

 

 

 

7

 

 

 

 

6

8

3

 

 

DX

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

 

 

4

5

 

 

 

 

 

 

 

DR

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

Figure 50. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1

98

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

Page 98
Image 98
Motorola TMS320C6711D warranty McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp =