Pwrd Field of the CSR Register, PD3 PD2 PD1 | Motorola TMS320C6711D

SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005

31	16

15	14	13	12	11	10	9	8
	Enable or	Enabled
Reserved	Non-Enabled	Enabled	PD3	PD2	PD1
Reserved	Non-Enabled	Interrupt Wake	PD3	PD2	PD1
	Interrupt Wake	Interrupt Wake
	Interrupt Wake
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7							0

Legend: R/W−x = Read/write reset value

NOTE: The shadowed bits are not part of the power-down logic discussion and therefore are not covered here. For information on these other

bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).

Figure 12. PWRD Field of the CSR Register

A delay of up to nine clock cycles may occur after the instruction that sets the PWRD bits in the CSR before the PD mode takes effect. As best practice, NOPs should be padded after the PWRD bits are set in the CSR to account for this delay.

If PD1 mode is terminated by a non-enabled interrupt, the program execution returns to the instruction where PD1 took effect. If PD1 mode is terminated by an enabled interrupt, the interrupt service routine will be executed first, then the program execution returns to the instruction where PD1 took effect. In the case with an enabled interrupt, the GIE bit in the CSR and the NMIE bit in the interrupt enable register (IER) must also be set in order for the interrupt service routine to execute; otherwise, execution returns to the instruction where PD1 took effect upon PD1 mode termination by an enabled interrupt.

PD2 and PD3 modes can only be aborted by device reset. Table 33 summarizes all the power-down modes.

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Motorola TMS320C6711D warranty Pwrd Field of the CSR Register, PD3 PD2 PD1

Contents

SPRS292A − October 2005 − Revised November Table of Contents Pages ADDITIONS/CHANGES/DELETIONS Revision HistoryMultichannel Buffered Serial Port Timing GDP and ZDP 272-PIN Ball Grid Array BGA PACKAGES† GDP and ZDP BGA packages bottom viewBottom View Description C6711D Device characteristicsCharacteristics of the C6711D Processor Hardware Features Internal Clock Device compatibility Digital Signal Processor Functional block and CPU DSP core diagram CPU DSP core description ST2 ST1DA1 DA2 TMS320C6711D Memory Map Summary Memory map summaryMemory Block Description Block Size Bytes HEX Address Range HEX Address Range Acronym Register Name Peripheral register descriptionsEmif Registers L2 Cache Registers HEX Address Range Acronym Register Name Comments Interrupt Selector RegistersDevice Registers Edma Parameter RAM† Quick DMA Qdma and Pseudo Registers† Edma Registers Gpio Registers PLL Controller RegistersHPI Registers McBSP0 McBSP1 Timer 0 and Timer 1 RegistersHEX Address Range Acronym Register Name Comments Timer McBSP0 and McBSP1 Registers Signal groups description CE0 CE3CE2 CE1 General-Purpose Input/Output Gpio Port GpioGP7EXTINT7 GP6EXTINT6 GP5EXTINT5 GP4EXTINT4 CLKOUT2/GP2 Device configurations at device reset Device Configurations BOOTMODE‡ Configuration GDP/ZDP Functional Description PINCLKMODE0 Eksrc Devcfg register descriptionBIT # Name Description Terminal Functions Terminal Functions PIN SignalIPD Description Name GDP IPU‡ ZDP IPD Description Name GDP IPU‡ ZDP Jtag Emulation Resets and Interrupts HD12 IPD Description Name GDP IPU‡ ZDP HOST-PORT Interface HPIUsed for transfer of data, address, and control Little Endian Decoded from the two lowest bits of the internal address Only one asserted during any external data accessEmif − ASYNCHRONOUS/SYNCHRONOUS Memory Control ¶ EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2 IPD Description Name GDP IPU‡ ZDP Emif − Address ¶ Multichannel Buffered Serial Port 1 McBSP1 IPD Description Name GDP IPU‡ ZDP Emif − Data ¶ GENERAL-PURPOSE INPUT/OUTPUT Gpio Module Multichannel Buffered Serial Port 0 McBSP0 RSV IPU RSVRSV IPD Supply voltage See Note Name GDP ZDP Supply Voltage PinsDvdd Cvdd GND Description Name GDP ZDP Supply Voltage PinsGround Pins VSS VSS PIN Signal TYPE† Description Name GDP ZDP Ground Pins VSS GND Description Name GDP ZDP Ground Pins Software Development Tools Development supportHardware Development Tools Device and development-support tool nomenclature Device supportFully qualified production device Technology Device Family Temperature Range Default 0 C to 90 CPrefix Device Speed Range Documentation support PCC DCC Pgie GIE CPU CSR register descriptionRevision ID Pwrd CPU ID CPU CSR Register Bit Field DescriptionPCC Ccfg Register Bit Field Description Cache configuration Ccfg register descriptionL2MODE Event DSP Interrupt Default Selector Module ControlInterrupt sources and interrupt selector DSP Interrupts Interrupt Selector Edma Channels Edma module and Edma selectorEdma Selector ESEL3 Register 0x01A0 FF0C ESEL1 Register 0x01A0 FF04 PLL and PLL controller MIN TYP MAX Unit PLL Lock and Reset TimesClkout Signals, Default Settings, and Control Enabled or Disabled PLL Clock Frequency Ranges†‡ Clock SignalGDPA−167, ZDPA-167 PLL Control/Status Register Pllcsr Pllcsr Register 0x01B7 C100 PLL Multiplier Control Register Pllm Pllm Register 0x01B7 C110 DxEN Oscillator Divider 1 Register OSCDIV1 OSCDIV1 Register 0x01B7 C124OD1EN GP7 GP6 GP5 GP4 GP2 General-purpose input/output GpioDIR Power-down mode logic PD3 PD2 PD1 Pwrd Field of the CSR Register Mode Power-supply sequencingCharacteristics of the Power-Down Modes System-level design considerations DSP Cvdd VSS GND Power-supply decouplingPower-supply design considerations Dvdd Ieee 1149.1 Jtag compatibility statement Example Boards and Maximum Emif Speed Emif device speed Emif Data Lines Pins Where Data Present Emif big endian mode correctnessED3124 BE3 ED2316 BE2 ED158 BE1 ED70 BE0 Reset Bootmode MIN NOM MAX Unit Recommended operating conditions‡IOH IOZ Parameter Test Conditions MIN TYP MAX Unit Output Under Test Signal transition levelsParameter Measurement Information Tester Pin Electronics = 0.3 tcmax† VIL max VUS max Ground AC transient rise/fall time specifications Timing parameters and board routing analysis Board-Level Timings Example see Figure Control Signals † Output from DSPOutput from DSP See Figure PLL Mode Bypass Mode UnitInput and Output Clocks Timing requirements for Clkin †‡§ Parameter GDPA-167Clkin CLKOUT3 −250 Timing requirements for ECLKIN† see FigureGDPA-167 ZDPA−167 −200 Are Asynchronous Memory TimingTiming requirements for asynchronous memory cycles†‡§ See −Figure AWE/SDWE/SSWE † Ardy Setup = Strobe = Not ReadyCEx BE30 EA212 Address ED310 Read Data AOE/SDRAS/SSOE † CEx BE30 EA212 Setup = Strobe = Not Ready Hold =AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy Timing requirements for synchronous-burst Sram cycles† SYNCHRONOUS-BURST Memory Timing ARE/SDCAS/SSADS† AOE/SDRAS/SSOE† AWE/SDWE/SSWE† CEx BE30BE1 BE2 BE3 BE4 EA212 ED310 Timing requirements for synchronous Dram cycles† see Figure Synchronous Dram Timing EA2113 Bank EA112 Column EA12 ED310 Read EclkoutAOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Write EclkoutEA2113 EA12 ED310 Dcab Eclkout Actv EclkoutCEx BE30 EA2113 Bank Activate EA112 Row Address EA12 ED310 AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† CEx BE30 EA212 EA12 ED310 Deac EclkoutCEx BE30 EA2113 Bank EA112 EA12 ED310 Refr Eclkout CEx BE30 EA212 MRS value ED310 MRS Eclkout Timing requirements for See Figure HOLD/HOLDA cycles† HOLD/HOLDA TimingHold Holda Eclkout Busreq Busreq Timing Timing requirements for reset†‡ see Figure Reset TimingCLKMODE0 = Clkin Eclkin Reset PhaseEmif Z Group† Emif Low Group† Group 2† Boot and Device Timing requirements for external interrupts† see Figure External Interrupt TimingEXTINT, NMI Hstrobe Hrdy HOST-PORT Interface TimingGDPA−167 Hstrobe HCS Hrdy HR/W Hhwil Hstrobe ‡ HCS HasHR/W Hhwil Hstrobe † HCS Has † Hrdy HD150 input 1st halfword 2nd halfwordHD150 input 1st half-word 2nd half-word −1 ¶ Multichannel Buffered Serial Port Timing Clkx Clks ClkrFSR int Bitn-1 Master Slave MIN MAX Timing requirements for FSR when Gsync = 1 see FigureClks FSR external CLKR/X no need to resync CLKR/X needs resync Clkx FSX MASTER§ Slave MINBit Bitn-1 MASTER§ Slave MIN MAX GDPA-167 McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Timing requirements for timer inputs† Timer TimingTINPx TOUTx Timing requirements for Gpio inputs†‡ GENERAL-PURPOSE INPUT/OUTPUT Gpio Port TimingGPIx GPOx TCK TDO TDI/TMS/TRST DTCKL-TDOV Delay time, TCK low to TDO validJtag TEST-PORT Timing Timing requirements for Jtag test port see Figure Mechanical Data Package thermal resistance characteristicsThermal resistance characteristics S-PBGA package for GDP Thermal resistance characteristics S-PBGA package for ZDP Qty Orderable Device Status Package Pins Package Eco PlanPackaging Information MSL Peak Temp Seating Plane 4204396/A 04/02 GDP S-PBGA-N272 Seating Plane 4204398/A 04/02 ZDP S-PBGA-N272 Important Notice